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Memory data quick reading device based on pre-reading and branch judgment mechanism

A technology for reading devices and memories, applied in the direction of input/output to record carriers, etc., to achieve good reusability, save operation time, and reduce operation time

Pending Publication Date: 2021-11-23
TIANJIN JINHANG COMP TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These factors limit the minimum time of the read cycle, that is, the read speed of the APB interface for the memory

Method used

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  • Memory data quick reading device based on pre-reading and branch judgment mechanism
  • Memory data quick reading device based on pre-reading and branch judgment mechanism
  • Memory data quick reading device based on pre-reading and branch judgment mechanism

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0088] For the details of the data transmission process in this embodiment, refer to the Summary of the Invention.

[0089] 1. In terms of system interface, the traditional connection mode is that the processor and the memory are connected through the APB bus interface, and the two perform data interaction through the APB bus; the present invention adds a preprocessing and branch judgment mechanism. Address signals, read and write signals are processed and sent to the memory, not through the APB bus.

[0090] 2. In terms of speed-up mechanism, the address signal and read-write signal are directly drawn from the processor through the preprocessing and branch judgment module, and the address and read-write signal are sent to the memory at the T1 stage of the APB bus, so that the memory starts data operation. The data is ready to be sent to the APB bus in the T2 cycle, which avoids the situation that the bus waits for the memory to process the data.

[0091] 3. In terms of the s...

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Abstract

The invention belongs to the technical field of computer storage, and particularly relates to a quick memory data reading device based on a pre-reading and branch judgment mechanism. The memory data quick reading device comprises a processor, an APB bus module, a memory and a preprocessing module, according to the characteristics of an APB bus interface access mechanism, a pre-reading mechanism and a branch judgment mechanism are utilized to realize command sending and data reading in advance for the memory, so that the waiting time of data sending out of the APB bus interface is shortened, the data reading speed is improved, the compatibility, usability and maintainability of a system are kept. The device has very important application significance.

Description

technical field [0001] The invention belongs to the technical field of computer storage, and in particular relates to a fast reading device for memory data based on a pre-reading and branch judgment mechanism. Background technique [0002] At present, the APB bus is widely used in embedded systems or ASIC chips for data access to the memory. The APB bus performs data reading operations through command sending and data latching. Due to the delay in the data interface of the memory itself, the APB bus interface There are certain restrictions on the data access speed of the memory, which cannot meet the requirements under certain usage conditions that require relatively high data read speed from the memory. [0003] Specifically, for a typical APB interface-connected memory architecture model, the connection relationship is as follows Picture 1-1 shown. [0004] Picture 1-1 A conventional connection mode of the APB bus interface is listed. In terms of the connection mode of ...

Claims

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Application Information

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IPC IPC(8): G06F3/06
CPCG06F3/0611G06F3/0638G06F3/0683
Inventor 李鑫朱天成曾永红李岩刘慧婕
Owner TIANJIN JINHANG COMP TECH RES INST
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