Communication method, system, device and medium of a distributed heterogeneous acceleration platform

Abstract

The application discloses a distributed heterogeneous acceleration platform communication method, system, device and medium. The method includes: after starting the collaborative acceleration task, the first target heterogeneous acceleration card in the distributed heterogeneous acceleration platform determines from the distributed heterogeneous acceleration platform by querying the information table corresponding to the collaborative acceleration task The second target heterogeneous acceleration card is generated; the target data packet is generated by the first target heterogeneous accelerator card according to the predefined packet format, and the target data packet is sent to the second target heterogeneous acceleration card through the PCIE interface An acceleration card: the second target heterogeneous accelerator card parses the target data packet according to the data packet format, and executes a corresponding read operation or write operation according to the parsing result, so as to complete the collaborative acceleration task. It can realize spontaneous data communication between multiple heterogeneous acceleration cards, and improve the ability of distributed heterogeneous accelerated computing.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a communication method, system, device and medium of a distributed heterogeneous acceleration platform. Background technique [0002] Currently, heterogeneous accelerator cards are widely used in data centers. For example, FPGA (Field Programmable GateArray, Field Programmable Gate Array) heterogeneous accelerator cards are equipped with standard PCIE (peripheral component interconnect express, which is a high-speed serial computer expansion Bus standard) interface, 10G or 100G network interface, used to build a distributed heterogeneous acceleration platform. In applications such as artificial intelligence and high-performance heterogeneous acceleration, multiple accelerator boards are often required to achieve a heterogeneous acceleration task through cooperation and division of labor. Therefore, communication and data transmission between different FPGA accelerator c...

AI Technical Summary

Problems solved by technology

In the prior art, data transmission between different accelerator cards is usually carried out through the network interface, but there are problems such as large data transmission delay and network packet loss when using the network interface, which cannot adapt to all scenarios

Most of the current PCIE interfaces of various acceleration cards are used for data interaction with the host (Host), and boards are completed using physically independent high-speed custom buses. How to use PCIE interfaces in heterogeneous acceleration platforms Data interaction and communication between different FPGA accelerator cards is still at the stage of the architecture solution dominated by the CPU, which reduces the efficiency of data transmission between heterogeneous accelerator cards

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