CV-QKD residual error code step-by-step elimination method and device based on cascade scheme

A CV-QKD and residual technology, applied in the application of multi-bit parity error detection coding, data representation error detection/correction, error correction/detection using block codes, etc., can solve problems such as limited effects, and achieve The effect of reducing the decoding FER and increasing the safe code rate

Pending Publication Date: 2022-08-09
NO 30 INST OF CHINA ELECTRONIC TECH GRP CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It is found through statistics that for some cases (for example, the case of long transmission distance), after the execution of this method, only some bits with decoding errors are corrected, and the effect of FER reduction is limited.

Method used

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  • CV-QKD residual error code step-by-step elimination method and device based on cascade scheme
  • CV-QKD residual error code step-by-step elimination method and device based on cascade scheme
  • CV-QKD residual error code step-by-step elimination method and device based on cascade scheme

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Experimental program
Comparison scheme
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Embodiment 1

[0037] see image 3 , the present invention proposes an embodiment of a method for step-by-step elimination of CV-QKD residual errors based on a cascading scheme. Elimination of residual errors in continuous variable quantum key distribution: The device for eliminating residual errors step by step is as follows:

[0038] It includes N residual error elimination units connected in cascade, and N is a positive integer; wherein, the first level residual error elimination unit is used for the first elimination of residual errors, and the i-th level residual error elimination unit is used for residual error elimination. The ith error elimination, i∈[2,N].

[0039] In this embodiment, the i-th threshold value set by the ith-level residual error elimination unit is smaller than the i-1-th threshold value set by the i-1-th residual error elimination unit.

[0040] In this embodiment, the structures of the first-stage residual error elimination unit and the i-th residual error elimin...

Embodiment 2

[0054] The present invention also provides a step-by-step method for CV-QKD residual error elimination based on a cascade scheme, which is applied to Embodiment 1, and the method includes the following steps:

[0055] 1) Set a larger threshold value δ in the residual error elimination unit 1 1 , and then run the unit for residual error cancellation.

[0056] 2) For the processing result of step 1), the residual error elimination unit 2 sets a threshold value δ 2 (δ 2 1 ) is processed again to further remove residual errors.

[0057] …

[0058] i) For the processing result of the i-1)th step, the residual error elimination unit i sets a threshold value δ i (δ i i-1 ) for processing, and the processing result will be used as the output of the entire residual error cancellation module.

[0059] In practical applications, a threshold value that can achieve the required residual error elimination effect can be selected as the threshold value in each of the above residual erro...

Embodiment 3

[0063] For ease of understanding, the present invention provides a more specific embodiment:

[0064] For a multi-sided LDPC code with a code rate of 0.1 and a code length of 1,000,000, under the condition that the signal-to-noise ratio SNR=0.163, a fixed-point number with a bit width of 10 (1 sign bit, 4 integer bits, 5 bits decimal places) to represent the intermediate data in the decoding process. Then, the error-corrected data frame is sent to the FPGA decoding system through the CV-QKD photoelectric system, and the maximum number of decoding iterations is set to 30. After the decoding is completed, the decoding result is sent back to the upper computer for statistical analysis of the decoding effect. After the actual test, when the error correction of 100 frames of data is completed, the typical value of the frame error rate is 0.98.

[0065] When using the error residual elimination method in the patent application number: 2021115885801.5 to process the decoding result...

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Abstract

The invention discloses a CV-QKD residual error code step-by-step elimination method and device based on a cascade scheme, the method sets threshold values in residual error code elimination units in cascade connection of the device, the first residual error code elimination unit sets a threshold value with a larger value, the second residual error code elimination unit sets a threshold value with a larger value, and the first residual error code elimination unit sets a threshold value with a larger value. And the error correction unit is used for correcting error bits with relatively large absolute values of the LLR values through decoding judgment, and then continuously reducing a threshold value in a subsequent residual error code elimination unit, and gradually correcting the remaining error bits, so that a syndrome obtained by multiplying code element bits after decoding by transpose of a matrix is the same as a syndrome generated by a sending end. According to the invention, the system decoding FER can be effectively reduced, and the security code rate of the CV-QKD system is improved.

Description

technical field [0001] The invention relates to the technical field of quantum keys, in particular to a method and device for step-by-step elimination of CV-QKD residual errors based on a cascade scheme. Background technique [0002] For the residual bit error problem, the existing solutions have some corresponding limitations. For example, in the patent application number: 2021115885801.5, for the absolute value of the Log Likelihood Ratio (LLR) value used by each variable node for the decoding decision after decoding, the proposed method for eliminating bit error residual requires The absolute value of the LLR value corresponding to the wrongly decoded bit should be small, and the absolute value of the LLR value corresponding to the correctly decoded bit is required to be larger, and then the correctly decoded bit can be summed by setting the threshold value. Decoding error bits are effectively distinguished (if the absolute value of the LLR value is less than or equal to...

Claims

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Application Information

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IPC IPC(8): H03M13/11
CPCH03M13/1125H03M13/1131
Inventor李扬周创徐兵杰黄伟马荔杨杰罗钰杰张帅胡金龙吴梅张亮亮
OwnerNO 30 INST OF CHINA ELECTRONIC TECH GRP CORP