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Data processing equipment and method

A data processing equipment and data processing technology, applied in the direction of electrical digital data processing, digital data processing components, instruments, etc., to achieve the effect of saving the space of operation code bits

Inactive Publication Date: 2005-09-07
ARM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Furthermore, in seeking to provide single cycle multiply performance, the additional burden of having to accommodate the requirements for saturation and associated scaling is such that the clock speed is adversely limited by the worst-case saturating multiply instruction

Method used

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  • Data processing equipment and method
  • Data processing equipment and method
  • Data processing equipment and method

Examples

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Embodiment Construction

[0044] figure 1Represents a portion of an integrated circuit 2 (similar to part of the ARM9TDMI microprocessor produced by ARM Ltd. of Cambridge, UK) comprising an instruction decoder 4 and processing logic 6 . The processing logic 6 is composed of many different, independent functional units. Register bank 8 stores data operand numbers (P, Q) to be processed. These words can be read from register bank 8 and provided to various other processing units within processing logic 6 via multiplexers 10 , 12 , 14 . An integer multiplier 16 is provided for performing signed integer multiplication, among other functions. An adder 18 is provided for performing an unsaturated multiply-accumulate operation and for converting the result of the multiplier from carry-save to two's complement format. A shifter 20 and an arithmetic logic unit 22 are also provided. The above-mentioned basic components of the processing logic 6 are generally known. Control signals 24 from instruction decoder...

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Abstract

In overall operation, in order to perform a Q15 multiply together with a Q31 accumulate operation, the processing proceeds as follows: Initially the Q15 values form the register bank (8) are read out upon bus A and bus B and fed as inputs to the single cylce integer multiplier (16). The result, which is in Q30-like form, is fed back to the register bank (8). On a subsequent processsing cycle one of the new instructions is executed (e.g. a QDADD instruction) to read out the Q30-like result of the multiply on the A bus and the Q31 accumulate value on the B bus. The Q30-like value is then left shifted by one or saturated by the shifting and saturating unit (26) and supplied as one input to the arithmetic logic unit (22).

Description

technical field [0001] The present invention relates to data processing systems. More specifically, the present invention relates to a data processing system for performing arithmetic operations suitable for performing saturated arithmetic operations. Background technique [0002] Many DSP algorithms use what are sometimes referred to as Q15 arithmetic and Q31 arithmetic. The Q15 number is an ordinary 16-bit two's complement integer (2's complement integer), but it is regarded as representing the integer divided by 2 15 . Because a 16-bit two's complement integer can represent the range -2 15 to +2 15 The number of -1, so a Q15 can represent the range from -1 to +(1-2 -15 ) number. [0003] Similarly, the Q31 number is an ordinary 32-bit two's complement integer and is considered to represent that integer divided by 2 31 , which can represent the range from -1 to +(1-2 -31 ) number. A QN number of (N+1) bits can be similarly defined for any other value of N. [000...

Claims

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Application Information

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IPC IPC(8): G06F7/544
CPCG06F2207/3812G06F7/5443G06F7/49921G06F7/49936
Inventor D·J·西尔
Owner ARM LTD
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