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Realizing device for embedded control path communication using FPGA completing optic transmission device

An embedded control and optical transmission technology, applied in transmission systems, digital transmission systems, electrical components, etc., can solve problems such as ECC communication blockage, heavy CPU load, and inability to complete DCC to ECC protocol conversion processing in real time, so as to improve stability sex, to solve the effect of blocking

Active Publication Date: 2007-06-27
ZTE CORP
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Problems solved by technology

[0008] In view of this, in order to solve the technical problems that the CPU load in the traditional method is too heavy, the DCC to ECC protocol conversion process cannot be completed in real time, and it is easy to cause ECC communication blockage, the present invention proposes a method of automatically processing ECC communication between optical transmission devices using FPGA full hardware device, by carrying out effective logic design to FPGA, single-board CPU only needs to complete some operations to FPGA initialization during initialization, such as registers are set, and the rest of the protocol processing work is automatically completed by FPGA hardware, which is the following of the present invention Technical solutions:

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  • Realizing device for embedded control path communication using FPGA completing optic transmission device
  • Realizing device for embedded control path communication using FPGA completing optic transmission device
  • Realizing device for embedded control path communication using FPGA completing optic transmission device

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Embodiment Construction

[0025] The invention utilizes the FPGA to realize the data exchange from the ECC main control board to the overhead processing place of the optical channel board, completes the HDLC protocol processing, and realizes the transmission of ECC and DCC data on both sides, and the whole transmission process does not need CPU real-time control. Instead of the traditional solution, the HDLC communication serial port of the CPU or the HDLC expander sends and receives serial data (hardware part), and then processes the process of forwarding between ECC data and DCC data (software part) in real time through software algorithms. The implementation plan is shown in the attached figure 2.

[0026] The realization of the whole scheme is divided into the following functional parts:

[0027] ECC_HDLC receiving: Receive the HDLC frame sent from the ECC main control board, analyze the ECC control information (several bytes of ECC information header), and then save the local data content in the c...

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Abstract

The invention discloses an ECC communication device between the two equipments for using field programmable logic device (FPGA) to realize optical transmission (SDH / SONET). The invention proposes the ECC communication device for using FPGA hardware to process SDH / SONET automatically, through the effective FPGA logic design, the veneer CPU only need to complete some initialization operation of FPGA, the rest tasks of the agreement processing are completed by the FPGA hardware automatically. The invention solves those technical problems, such as CPU overloading in the traditional way, no real-time to complete the conversion from DCC protocol to ECC protocol and easy ECC communication blocking, and raises ECC communications stability of the fiber transmission network.

Description

technical field [0001] The invention relates to the technical field of synchronous optical network communication, in particular to a device for realizing ECC (Embedded Control Channel) communication between optical transmission (SDH / SONET) equipment by using a field programmable logic device (FPGA). Background technique [0002] In the circuit board of one or more line interfaces of traditional optical transmission equipment, the DCC processing unit formed by the FPGA device completes the overhead sending and receiving connection with the framer, and processes one or more channels of D1~D12 words in the overhead All or part of the section, synthesize a data packet conforming to the HDLC protocol and send it to the DCC serial bus, and then the next-level device completes the protocol conversion from the DCC data packet format to the ECC data packet format. There are two main conversion methods. The implementation method is shown in Figure 1: [0003] Method 1 uses the ready-...

Claims

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Application Information

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IPC IPC(8): H04L12/56H04L29/06H04L12/937
Inventor 刘毅桑吉淼
Owner ZTE CORP
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