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A fpga implementation method of lfmcw radar mtd processing

An implementation method, radar technology, applied in the input/output process of data processing, electrical digital data processing, program control, etc., can solve problems such as ease of use, limited storage resources, and inability to cache echo data, etc., to improve flexibility, Improve reliability and save hardware resources

Active Publication Date: 2022-06-17
HARBIN ENG UNIV
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Problems solved by technology

However, FPGA also has its own limitations. First, the internal storage resources of FPGA are limited, and it cannot cache a large amount of echo data by itself; secondly, FPGA has limited computing power, and it is difficult to perform complex multiplication operations like DSP. The same ease; and in practical applications, it is often necessary to dynamically change the number of MTD points (that is, the number of accumulation cycles) according to the observation distance and target speed.

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  • A fpga implementation method of lfmcw radar mtd processing
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  • A fpga implementation method of lfmcw radar mtd processing

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Embodiment Construction

[0033] The present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0034]The method proposed by the present invention utilizes DDR3 SDRAM to cache radar echo data, performs address division and segmental read and write on it through FPGA to realize fast / slow time dimension conversion of echo data, and utilizes FFT IP core to realize slow time dimension data conversion. Finally, the fixed-point calculation results are converted into single-precision floating-point numbers to ensure the dynamic range and accuracy of the calculation results. The ModelSim simulation and hardware test in this paper are based on the FPGA device XC7V585T-2FFG1761I of the Xilinx V7 series, and the development platform is Vivado2019.2; 64-bit memory with a total capacity of 2GB. But this method also works for other Xilinx FPGA devices that support the DDR3 interface.

[0035] The steps of the present invention are as follows:...

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Abstract

The invention provides an FPGA implementation method for LFMCW radar MTD processing. The invention proposes a method that can realize LFMCW radar MTD processing on FPGA, aiming at the requirements of LFMCW radar system for real-time performance and high throughput of MTD processing. This method can make full use of the parallel processing capability of FPGA and the high efficiency of pipeline processing and ping-pong operation processing, and cooperate with the double data rate and large capacity of DDR3 SDRAM to solve the bottleneck problem of DSP processing speed and FPGA storage space. Finally, the validity and reliability of the method are proved by ModelSim simulation and actual system test.

Description

technical field [0001] The invention belongs to the field of radar signal processing, and in particular relates to a moving target detection (MTD) processing method applied to a linear frequency modulated continuous wave (LFMCW) radar system, in particular to a method based on a field programmable logic gate array (FPGA). , the method of real-time MTD processing with variable number of points. Background technique [0002] The transceiver antenna of LFMCW radar requires high isolation, and the performance of early microwave devices is limited, so it is not widely used. In recent years, with the continuous development of electronic technology, there are more and more application scenarios of LFMCW radar, and the advantages are more and more obvious. LFMCW radar has no blind spot, and the transmit power is smaller and the probability of interception is lower under the same detection distance index. It is widely used in small target detection, security of airports and militar...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01S7/41G05B19/042G06F3/06
CPCG01S7/415G05B19/0423G06F3/0608G06F3/0611G06F3/0656G06F3/0679
Inventor 郭立民莫禹涵禹永植
Owner HARBIN ENG UNIV
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