35 results about "DDR3 SDRAM" patented technology

A memory device can be directly mounted on a motherboard supporting DDR3 SDRAM, and then the memory device have advantages of the fly-by bus topology and the T branch topology established by the joint electron device engineering council (JEDEC). Thus, the system performance of a desktop computer in a unit interval can be enhanced.

A method for manufacturing a dynamic random access memory device is provided. The method includes fabricating a dynamic random access memory device having a plurality of memory cells. Each of the memory cells has a refresh characteristic that meets or exceeds a refresh specification provided for a DDR3 SDRAM device or a DDR4 SDRAM device. The method includes testing the dynamic random access memory device. The testing includes determining the refresh characteristic for each of the memory cells, classifying each of the memory cells as a good memory cell or a bad memory cell based upon the refresh characteristic, identifying each of the bad memory cells, and storing an address location for each of the bad memory cells. The method then includes transferring the address location for each of the bad memory cells into an address match table.

The present invention relates to a memory device, which can be directly arranged on any motherboard in the prior art which can support the third-generation dual-channel synchronous dynamic random access memory DDR3 SDRAM, so as to integrate the advantages of the fly-by bus bracket and the T-shaped branch bracket, which are prepared in the JEDEC. Therefore, the memory device can improve the systemefficiency of the table computer in unit time.

The invention relates to a five-dimensional dynamic stereoscopic clutter map implementation method based on a DDR3-SDRAM. According to the five-dimensional dynamic stereoscopic clutter map implementation method, reading and writing control over the DDR3-SDRAM is achieved through an FPGA, and then a five-dimensional dynamic stereoscopic clutter map is established. The method comprises the following steps that (a) reading operation is conducted on the DDR3-SDRAM, and clutter data are read out; (b) a clutter map is updated through a recursive filter, and data conversion is conducted; (c) the updated cluster data are rewritten to the corresponding position of the DDR3-SDRAM, updating of the cluster map is completed, and a clutter map is established. Compared with a traditional cluster map implementation method, the five-dimensional dynamic stereoscopic clutter map implementation method based on the DDR3-SDRAM is characterized in that a clutter area is finely divided, and besides traditional distance division, direction division and pitching division, a PRF mode and clutters of a full-Doppler channel are also divided. Clutter data are specially processed, the storage capacity of the clutter map is doubled.

The present invention relates to a data pass control device for masking a ringing of a data strobe that occurs when a write operation in a DDR SDRAM is completed. The data pass control device for masking the write ringing in the DDR SDRAM can be advantageously used for masking only a section with the ringing problem during the write operation, so that any unnecessary operations during the write operation can be eliminated and a more stable write operation can be realized by eliminating a write fail.

The invention discloses an airborne wireless access point (AP) device. The airborne wireless AP device comprises a power supply module, an AP main board, an interface board, an Ethernet airspace connector, a power supply aerospace connector and an antenna, wherein the antenna is connected with the AP main board, and the power supply module, the AP main board, the Ethernet aerospace connector and the power supply aerospace connector are respectively connected with the interface board. The AP main board comprises a processor, and an Ethernet interface unit, a discrete magnate control unit, a radio frequency unit, a DDR3 SDRAM memory, a flash memory, a JTAG interface and a serial port, which are respectively connected with the processor, and the AP main board also comprises a power supply system unit, and the power supply system unit is used for powering each device on the AP main board. The airborne wireless AP device can implement WIFI connection in a cabin and has advantages of improving the user experience. The application stability is good, and the practicability is high.

The invention provides a function verification method and platform for a DDR3 SDRAM (double data rate 3 synchronous dynamic random access memory) controller. The function verification method comprises steps as follows: adopting a test case to detect correctness of user read-write operation, specific user interface timing sequences or signals; adopting a port monitoring module designed with layering and object oriented technologies to detect correctness of DDR3 SDRAM port signals. According to the invention, the design of the port monitoring module adopts layering and object oriented design methods, so that various timing sequence constraints at a DDR3 SDRAM port are effectively organized in the aspects of time and space, the probability of omission is low, and maintenance and upgrading are facilitated.

The embedded guide star processing system relates to an embedded guide star processing system for space targets, which solves the problem that the existing image acquisition and processing system is difficult to cope with the huge amount of real-time data, and the guide star is difficult, so that the main field of view cannot be aligned with the space for a long time. Target observation and other issues, including image acquisition module and guide star calculation module, the guide star calculation module adopts the guide star processing system with FPGA and DSP heterogeneous processor architecture, and the image acquisition module collects the sCMOS camera video signal in real time And stored in DDR3 SDRAM, and then the image data in DDR3 SDRAM is sent to the guide star calculation module; it provides powerful image processing and calculation analysis capabilities, can identify space targets, obtain their precise center of mass positions, and calculate the error The vector is converted into the actual amount of the telescope missing the target, which is fed back to the pointing control system of the astronomical telescope. The embedded guide star processing system improves the stability and accuracy of the guide star, achieving long-term observation of the target.

The invention relates to an FPGA-based USB data real-time monitoring system and method, belonging to the technical field of electronics and communication. The present invention includes FPGA chip, USB transceiver module I, USB transceiver module II, DDR3 SDRAM memory; FPGA chip includes: ULPI data transceiver module I, ULPI data transceiver module II, ULPI control module I, ULPI control module II, data temporary memory module and FPGA signal processing and coordination module. In the present invention, the FPGA is used for relay, and the data on the USB bus can be unpacked, stored, and forwarded after being connected to the USB transmission line without a PC, so as to realize real-time monitoring and collection of non-invasive USB data from the data level. .

The present invention is a data acquisition system based on high-speed analog-to-digital conversion and time-to-digital conversion technology, belonging to the field of electronic technology, including a front-end signal conditioning module, which includes a discrimination circuit and a differential conditioning circuit; including a TDC chip and an ADC chip respectively The data acquisition module that receives the signal processed by the discrimination circuit and the differential conditioning circuit; the FPGA timing control unit connected to the TDC chip and the ADC chip respectively, and the FPGA timing control unit reads the data of the TDC chip and the ADC chip, and communicates with the DDR3 SDRAM memory and PCIE Connected to the bus, connected to the computer through the PCIE bus; used to input the trigger signal to the discrimination circuit when the ion enters the time-of-flight mass analyzer, and input the trigger signal to the pulse generator of the FPGA timing control unit, and the FPGA timing control unit receives After the trigger signal is received, a control sequence is generated to enable the ADC chip and the TDC chip to collect at the same time. The system can obtain the data collected by the ADC and TDC at the same time, and take advantage of the advantages of ADC collection and TDC collection.