35 results about "DDR3 SDRAM" patented technology

The present invention discloses an FPGA (Field Programmable Gate Array) realization method of a SAR (Synthetic Aperture Radar) signal processing algorithm, belonging to the radar imaging and digital signal processing technology field. The method comprises: building hardware configuration of an upper computer, an Ethernet data communication module, an algorithm processing module, a DDR3 SDRAM and a control module thereof, a data selection module, a reset module, a clock management module, the algorithm processing module is provided with a polar coordinate format imaging algorithm of dechirp signals based on the Chirp Scaling principle and a two-dimensional self-focusing algorithm, and therefore the problem of high resolution ratio imaging of a mini-type SAR system and the ultrahigh resolution imaging processing of SAR etch signals are realized.

The invention discloses a data processing board system based on a standard AMC platform, including a power supply module, an intelligent management unit, a processor unit, a logic unit, an SRIO switching module and a Gigabit Ethernet switching module, and the power supply module is used to supply power to the entire board , the intelligent management unit communicates with the processor unit, the logic unit is connected to the processor unit through the SRIO switch module, and the processor unit is also connected to the Gigabit Ethernet switch module. The processor unit includes a P2020 processor produced by Freescale, P2020 The processor is externally connected with 64-bit DDR3 SDRAM, and 3 FLASH chips are connected by CPLD logic. The invention improves the data processing ability through the P2020 processor, and increases the signal exchange speed by combining the SRIO switching module and the Gigabit Ethernet switching module. The P2020 processor is externally connected with 4 pieces of 64-bit 512MBx16 DDR3 SDRAM chips and 3 pieces of FLASH, so that the present invention has strong data storage performance and helps to strengthen the data processing and transmission capabilities of the P2020.

The invention relates to a five-dimensional dynamic stereoscopic clutter map implementation method based on a DDR3-SDRAM. According to the five-dimensional dynamic stereoscopic clutter map implementation method, reading and writing control over the DDR3-SDRAM is achieved through an FPGA, and then a five-dimensional dynamic stereoscopic clutter map is established. The method comprises the following steps that (a) reading operation is conducted on the DDR3-SDRAM, and clutter data are read out; (b) a clutter map is updated through a recursive filter, and data conversion is conducted; (c) the updated cluster data are rewritten to the corresponding position of the DDR3-SDRAM, updating of the cluster map is completed, and a clutter map is established. Compared with a traditional cluster map implementation method, the five-dimensional dynamic stereoscopic clutter map implementation method based on the DDR3-SDRAM is characterized in that a clutter area is finely divided, and besides traditional distance division, direction division and pitching division, a PRF mode and clutters of a full-Doppler channel are also divided. Clutter data are specially processed, the storage capacity of the clutter map is doubled.

The invention discloses a DDR-based high-efficiency matrix transposition processing method. The method comprises the following steps of matching a write RAM and a read RAM with an IP core of a DDR3 SDRAM; wherein a to-be-transposed matrix is a 128 * 128 matrix with 64 bits of single data, and data of each row of the to-be-transposed matrix is taken as a small matrix; writing 16 data in each activesignal in the writing operation process; reading 8 * 16 pieces of data by each active signal in the reading operation process; and performing reading in DDR according to a same inter-row and data cyclic skip rule, so that the occurrence of row active signals is reduced as much as possible. According to the invention, the problem that the overall processing rate of the system is reduced due to the jump access of the DDR SDRAM in large-order matrix transposition is solved. By the matrix partitioning technology, on the basis that the writing rate is reduced to a small extent, the reading rate is greatly increased, the DDR reading and writing rate is balanced when a matrix is transposed, and therefore the average DDR reading and writing efficiency is improved.

The invention relates to an SDRAM bridge circuit, comprising a first module, a second module and a PHY module, wherein the first module is used for analyzing SDRAM access commands sent by a controller, the second module is used for converting the SDRAM access commands into commands which are acceptable to the PHY module, the PHY module is used for accessing a memory by using the commands which are acceptable to the PHY module, and the memory and the controller are different in SDRAM type. According to the invention, the SDRAM controller can be allowed to realize the access to the DDR3 SDRAM to carry out data access through the bridge circuit; compared with replacing or redeveloping chips of the integrated SDRAM controller, the circuit modification is small, the development period is short, the cost is low, and the bridge circuit is well compatible with the original system.

The present invention relates to data storage technology. The present invention solves the problem that the existing same system is easy to cause memory overflow and collapse when using new memory and/or new memory from different manufacturers in different temperature environments, and provides a self-adaptive new memory matching data strobe pulse The method, and its technical solution can be summarized as: detecting the high-order and low-order DQS/DQ phase points of each DDR SDRAM at each initialization to obtain an effective point, and then selecting the intermediate value to preset as an environmental parameter. The invention has the beneficial effects of stable operation and is suitable for systems using DDR2 SDRAM and/or DDR3 SDRAM.

The invention discloses a multipurpose low-power control device and a multipurpose low-power control method for dynamic characteristic tests. The multipurpose low-power control device comprises an ARM [advanced RISC (reduced instruction set computer) machine] processor, an OLED (organic light emitting diode) display module, a DDR3 SDRAM (double data rate 3 synchronous dynamic random access memory), an SPI (serial peripheral interface) Flash storage module, an eMMC (embedded multimedia card) storage module, an SD (secure digital) card storage module, a GPS (global positioning system) positioning module, a wire communication module, a wireless communication module, a charge and discharge management module, a power supply module and a peripheral module. Battery charge and discharge can be managed by the charge and discharge management module, and external AC adapter power supply and battery power supply paths can be dynamically switched over according to requirements of systems. The multipurpose low-power control device and the multipurpose low-power control method have the advantages that the problem of poor compatibility of existing master control and data acquisition cards can be solved by the aid of the multipurpose low-power control device and the multipurpose low-power control method, and the multipurpose low-power control device and the multipurpose low-power control method are conveniently compatible with existing high-precision universal data acquisition cards.

The invention discloses a double-channel high-speed analog digital signal collecting and processing board card. The board card comprises an FPGA, a DSP, four DDR3 SDRAMs, two SPI EEPROMs, two SPI FLASHs, two differential amplifiers, an analog-digital converter, an NAND FLASH, an Ethernet transceiver, a PCI-express connector, a clock selecting chip and clock managing chips, wherein the clock selecting chip and the clock managing chips are connected with clocks respectively. The mature and reliable components are adopted in the design, the normative circuit design is supplemented, and accuracy and efficiency of signal collecting and processing are ensured. The standard 3U board card size is adopted and can be matched with a standard 3U case. The standard PCI-express connector is adopted to be in butt joint with a case or a board card with a corresponding interface conveniently to achieve data interaction between the signal collecting and processing board card and other structures of a system.

The invention relates to display interfaces, in particular to an FPGA-based digital video display interface module and a communication method thereof, through which the problem of the conventional display interface that an insufficient cache rate causes smearing of an image displayed on equipment is solved. The FPGA-based digital video display interface module comprises an FPGA, a DDR3-SDRAM, a CH7301C chip, and a DVI-I interface, wherein the FPGA is connected with both the DDR3-SDRAM and the CH7301C chip, the CH7301C chip is connected with the DVI-I interface, and the DVI-I interface is connected with a display. The FPGA-based digital video display interface module and the communication method thereof provided by the invention are applicable to aerospace, military, medicine and other fields.

The invention discloses an airborne wireless access point (AP) device. The airborne wireless AP device comprises a power supply module, an AP main board, an interface board, an Ethernet airspace connector, a power supply aerospace connector and an antenna, wherein the antenna is connected with the AP main board, and the power supply module, the AP main board, the Ethernet aerospace connector and the power supply aerospace connector are respectively connected with the interface board. The AP main board comprises a processor, and an Ethernet interface unit, a discrete magnate control unit, a radio frequency unit, a DDR3 SDRAM memory, a flash memory, a JTAG interface and a serial port, which are respectively connected with the processor, and the AP main board also comprises a power supply system unit, and the power supply system unit is used for powering each device on the AP main board. The airborne wireless AP device can implement WIFI connection in a cabin and has advantages of improving the user experience. The application stability is good, and the practicability is high.

The invention discloses a double-screen different-image graphic generating system. The system comprises a comprehensive programmable device and a DDR3 SDRAM frame memory device which are connected, wherein the comprehensive programmable device comprises an ARM processor, a multi-port DDR3 SDRAM controller, a first DDR3 SDRAM frame memory reading and writing module, a first data conversion module, a second data conversion module, a second DDR3 SDRAM frame memory reading and writing module, a thirddata conversion module, a fourth data conversion module and a timing sequence generation module; the DDR3 SDRAM frame memory device comprises a first buffer module, a second buffer module, a third buffer module, a fourth buffer module, a fifth buffer module and a sixth buffer module. The double-screen different-image graphic generating system is characterized by high circuit integration level, low power consumption and small size; synchronous output of double-screen different-image frames can be achieved, and the double-screen frames can be spliced into a complete frame; data bandwidth is high, and processing speed is high; graphic generation efficiency is high, and dynamic frame display is smooth; compatibility is high, and the system can support various high-resolution frames.

The invention provides an FPGA implementation method for LFMCW radar MTD processing, and provides a method capable of realizing the LFMCW radar MTD processing on an FPGA aiming at the requirements ofan LFMCW radar system for the real-time performance and high throughput rate of the MTD processing. According to the method, the parallel processing capability of the FPGA and the high efficiency of pipeline processing and ping-pong operation processing can be fully utilized, and in cooperation with the characteristics of double data rate and large capacity of the DDR3 SDRAM, the bottleneck problems of the processing speed of the DSP and the storage space of the FPGA are solved, and finally, effectiveness and reliability of the method are proved through ModelSim simulation and actual system testing.

The invention discloses a high-speed analog quantity acquisition board card based on FPGA + MCU. The high-speed analog quantity acquisition board card comprises a signal conditioning circuit, an ADC sampling circuit, an FPGA chip, an MCU processor and a communication module. The FPGA chip comprises an ADC controller, a front end FIFO memory, a DDR3 controller, a rear end FIFO memory and a DDR3 SDRAM memory. The signal conditioning circuit comprises a differential circuit, an 8-bit dial switch, an instrument amplifier, a low-pass filter circuit and a voltage follower circuit, and the signal conditioning circuit receives analog signals sent by sending equipment, filters noise of the analog signals, conditions the analog signals into +/-10V analog signals and outputs the +/-10V analog signals. According to the invention, the signal conditioning circuit is used for differential input; the voltage drop on the ground wire can be compensated; the input ranges of +/-50V, +/-25V and +/-12.5 V signals and the three low-pass filtering cut-off frequencies of 20Hz, 300Hz and 10kHz can be configured by toggling corresponding switches of the 8-bit dial switch, so that the detection of signals indifferent ranges and the filtering of noise in different frequency bands are realized.

The invention provides a pipelined digital radio frequency memory module. A delay control logic unit generates an address written from SDRAM write data FIFO to DDR3 SDRAM according to a set delay time parameter. The DDR3 SDRAM is read out to an address of SDRAM read data FIFO The difference between these two addresses equal to delay time divided by DDR3 SDRAM read and write clock cycles A control SDRAM controls IP to read a nuclear time sheet to read SDRAM write data FIFO data and writes into data of SDRAM read data FIFO. At the position of written labeling of SDRAM read data FIFO, the time sheet is distributed to read and write SDRAM writedata FIFO data. At the position of written emptiness of SDRAM read data FIFO, the time sheet is distributed to read and write SDRAM writedata FIFO data.

The invention relates to a phased array radar signal processing system-on-chip based on an SIP technology. The phased array radar signal processing system-on-chip comprises a substrate, an FPGA chip, a DSP chip, a first clock chip, a second clock chip, a DAC chip, a plurality of ADC chips, a plurality of DDR3 SDRAM chips and a FLASH EEPROM chip. The SIP technology is adopted, bare chips of all chips are reasonably placed on the high-density ceramic circuit substrate with the cavity, and all the chips are connected through lines in the substrate. While basic functions of the phased array radar are completed, minimization and low power consumption processing is carried out on the system, and the stability of the system is improved.

The invention discloses an HDM-to-eDP interface conversion device and interface conversion method based on an FPGA. An FPGA module in the device comprises an HDMI RX module, a MicroBlaze soft core module, a scaler scaling module, an FIFO module, a DDR3 bus control module, a DDR3 IP core module, a 4K image data fusion module, a 4K high-definition time sequence control module and an eDP TX module. The HDMI RX module receives a video image from the PC host; the HDMI RX module converts the HDMI video image into an RGB format; the scaler scaling module amplifies the resolution of the video image in the RGB format to 4K, and the resolution is stored by the FIFO module; when the number of the stored data of the FIFO module reaches a preset pixel point number, the currently stored pixel point is stored into the DDR3 SDRAM; the 4K image data fusion module reads data from the DDR3 SDRAM for preprocessing, then the data is converted into an eDP signal by the 4K high-definition sequential control module, and the eDP signal is sent to the high-definition display by the eDP TX hardware interface. According to the invention, the display speed of the 4K high-definition liquid crystal display is high.

The invention relates to a USB data real-time monitoring system and method based on FPGA, and belongs to the technical field of electronics and communication. The invention comprises an FPGA chip, a USB transceiver module I, a USB transceiver module II and a DDR3 SDRAM memory. The FPGA chip includes a ULPI data transceiver module I, a ULPI data transceiver module II, a ULPI control module I, a ULPI control module II, a data temporary storage module and an FPGA signal processing and coordination module; As that FPGA of the invention is used as a relay, the data on the USB bus can be unpacked, stored and forwarded after the USB transmission line is accessed without a PC, so that the non-invasive USB data real-time monitor and collection from the data level can be realized.