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Phased array radar signal processing system-level chip based on SIP (Session Initiation Protocol) technology

A phased array radar and system-level chip technology, applied in the electronic field, can solve problems such as insufficient stability, high power consumption, and large area, and achieve the effects of low power consumption, increased integration, and improved stability

Pending Publication Date: 2022-07-22
XIDIAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as the functions of the radar signal processing system become more and more complex, there are more and more devices, the miniaturization of the system, and the trend of modularization are far faster than Moore's Law. The traditional radar signal processing system uses chips and PCB boards. Design, while the area is large, the power consumption is relatively high, and the stability is not enough, it is becoming more and more difficult to apply to warheads or small carriers
Moreover, at present, most radar signal processing systems mostly use foreign chips. Under such a severe background, they are often controlled by others, so the localization of chips is also a problem we have to face today.

Method used

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  • Phased array radar signal processing system-level chip based on SIP (Session Initiation Protocol) technology

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Embodiment 1

[0034] In 1961, Texas Instruments invented the world's first integrated circuit, marking the third generation of computers. With the development of semiconductor circuits, how to break through the limitations of Moore's Law has become a major problem, especially in today's highly integrated system and increasingly complex environment, the original board-level radar signal processing system is affected by price, power consumption, Stability limitations, etc.

[0035] Based on this, the present invention provides a phased array radar signal processing system-level chip based on SIP technology, please refer to figure 1 , figure 1 This is a schematic structural diagram of a phased array radar signal processing system-level chip based on SIP technology provided by an embodiment of the present invention. The present invention provides a phased array radar signal processing system-level chip based on SIP technology. Signal processing SoCs include:

[0036]A substrate, an FPGA (Fie...

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Abstract

The invention relates to a phased array radar signal processing system-on-chip based on an SIP technology. The phased array radar signal processing system-on-chip comprises a substrate, an FPGA chip, a DSP chip, a first clock chip, a second clock chip, a DAC chip, a plurality of ADC chips, a plurality of DDR3 SDRAM chips and a FLASH EEPROM chip. The SIP technology is adopted, bare chips of all chips are reasonably placed on the high-density ceramic circuit substrate with the cavity, and all the chips are connected through lines in the substrate. While basic functions of the phased array radar are completed, minimization and low power consumption processing is carried out on the system, and the stability of the system is improved.

Description

technical field [0001] The invention belongs to the field of electronic technology, and relates to a phased array radar signal processing system-level chip based on SIP technology. Background technique [0002] Since Moore's Law was proposed, it has both pointed out the way and created constraints for the development of the semiconductor industry. Now the semiconductor industry is iterating roughly every 18 months, the number of components on fixed-size boards is also increasing, and the board area is also shrinking. However, as the functions of radar signal processing systems become more and more complex, there are more and more devices, the miniaturization of the system, and the trend of modularization develops faster than Moore's Law. Traditional radar signal processing systems use chips and PCB boards for processing. Design, while the area is large, the power consumption is relatively high, and the stability is not enough, it is more and more difficult to apply to warhe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01S7/41
CPCG01S7/414G01S7/418
Inventor 赵佳琪张宇全英汇肖国尧冯浩轩吴征程
Owner XIDIAN UNIV
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