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SDRAM bridge circuit

A bridge circuit and circuit-associated clock technology, which is applied in the field of access control, can solve the problems of large circuit changes, long development cycle, and heavy workload, and achieve the effect of small circuit changes, short development cycle, and good compatibility

Inactive Publication Date: 2012-06-27
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] When replacing or modifying an existing chip to integrate a new PHY, it will "touch the whole body", resulting in a large amount of circuit changes, a long development cycle, high costs, and incompatibility with the original system
For example, when it is necessary to replace the central processing unit CPU with external SDRAM with a CPU with external DDR3 SDRAM, the operating system will also be replaced, and all software will be redeveloped; when the scale of the chip is large, the overall workload of redevelopment will be huge and the cost will be high

Method used

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Embodiment Construction

[0023] figure 1 It is a schematic diagram of the SDRAM bridge circuit of the embodiment of the present invention. Such as figure 1 As shown, the SDRAM bridge circuit includes a first module 110 , a second module 120 and a DDR3 physical interface (hereinafter referred to as PHY) module 130 . The three modules jointly realize the process of converting SDRAM controller access commands into accessing DDR3 SDRAM memory.

[0024] The first module 110, also called the SDRAM access command analysis and data transceiving module, is responsible for analyzing the access command sent by the SDRAM controller, and transmitting and receiving signals between the external SDRAM controller. Specifically, the module 110 parses the access command, and sends the parsed access command and the data to be written to the command and data conversion module 120; at the same time, receives the read data sent by the second module 120, and sends it to the external SDRAM controller.

[0025] The second ...

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PUM

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Abstract

The invention relates to an SDRAM bridge circuit, comprising a first module, a second module and a PHY module, wherein the first module is used for analyzing SDRAM access commands sent by a controller, the second module is used for converting the SDRAM access commands into commands which are acceptable to the PHY module, the PHY module is used for accessing a memory by using the commands which are acceptable to the PHY module, and the memory and the controller are different in SDRAM type. According to the invention, the SDRAM controller can be allowed to realize the access to the DDR3 SDRAM to carry out data access through the bridge circuit; compared with replacing or redeveloping chips of the integrated SDRAM controller, the circuit modification is small, the development period is short, the cost is low, and the bridge circuit is well compatible with the original system.

Description

technical field [0001] The invention relates to access control of synchronous dynamic random access memory. Background technique [0002] Synchronous Dynamic Random Access Memory (SDRAM) is widely used in various electronic products, and is constantly being updated. So far, a large number of commercial products of successive generations include SDRAM, DDR SDRAM, DDR2SDRAM and DDR3SDRAM (the full name of DDR is Double Data Rate, which means double data rate). The earlier SDRAM has withdrawn from the mainstream or even ceased production, and more and more products use a new generation of memory such as DDR3SDRAM. [0003] The SDRAM accepts the access of the SDRAM controller, and the DDR / DDR2 / DDR3 SDRAM accepts the access of the controller and the PHY (Physical Interface, physical layer interface) to realize data access. Each generation of memory can only be physically connected to the corresponding controller or PHY, and the generations cannot be used universally. For exampl...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/4063
Inventor 魏先锋王斐昊
Owner HUAWEI TECH CO LTD
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