FPGA implementation method for LFMCW radar MTD processing

Abstract

The invention provides an FPGA implementation method for LFMCW radar MTD processing, and provides a method capable of realizing the LFMCW radar MTD processing on an FPGA aiming at the requirements ofan LFMCW radar system for the real-time performance and high throughput rate of the MTD processing. According to the method, the parallel processing capability of the FPGA and the high efficiency of pipeline processing and ping-pong operation processing can be fully utilized, and in cooperation with the characteristics of double data rate and large capacity of the DDR3 SDRAM, the bottleneck problems of the processing speed of the DSP and the storage space of the FPGA are solved, and finally, effectiveness and reliability of the method are proved through ModelSim simulation and actual system testing.

Description

technical field [0001] The invention belongs to the field of radar signal processing, and in particular relates to a moving target detection (MTD) processing method applied to a linear frequency modulated continuous wave (LFMCW) radar system, in particular to a method based on a field programmable logic gate array (FPGA). , the method of real-time MTD processing with variable number of points. Background technique [0002] The transceiver antenna of LFMCW radar requires high isolation, and the performance of early microwave devices is limited, so it is not widely used. In recent years, with the continuous development of electronic technology, there are more and more application scenarios of LFMCW radar, and the advantages are more and more obvious. LFMCW radar has no blind spot, and the transmit power is smaller and the probability of interception is lower under the same detection distance index. It is widely used in small target detection, security of airports and militar...

AI Technical Summary

Problems solved by technology

However, FPGA also has its own limitations. First, the internal storage resources of FPGA are limited, and it cannot cache a large amount of echo data by itself; secondly, FPGA has limited computing power, and it is difficult to perform complex multiplication operations like DSP. The same ease; and in practical applications, it is often necessary to dynamically change the number of MTD points (that is, the number of accumulation cycles) according to the observation distance and target speed.

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