Pipelined digital radio frequency memory module

A technology of memory module and digital radio frequency, which is applied in the direction of electrical digital data processing, instrumentation, radio wave measurement system, etc. It can solve the problems of radar signal time overlap and calculation error of radar pulse release time, etc.

Inactive Publication Date: 2019-09-27
NANJING GUORUI ANTAIXIN TECH
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  • Summary
  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The traditional DRFM uses the detection result of the radar pulse envelope as the storage time of the radar pulse signal, and then releases the stored radar pulse signal when the release time arrives. This method is relatively simple in control, but if the storage frequency When there is more than one radar signal in the bandwidth, there will be a problem that the radar signals with different pulse repetition periods PRI overlap in time, resulting in an error in the calculation of the radar pulse release time

Method used

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  • Pipelined digital radio frequency memory module
  • Pipelined digital radio frequency memory module
  • Pipelined digital radio frequency memory module

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Embodiment Construction

[0021] The present invention will be described in further detail below.

[0022] Such as figure 1 As shown, the present invention provides a kind of pipelined digital radio frequency memory module, comprises field programmable gate array FPGA, the third generation double rate synchronous dynamic random access memory DDR SDRAM, and described FPGA comprises pipelined DRFM control unit, described The pipeline DRFM control unit includes delay control logic unit, SDRAM write data FIFO, SDRAM read data FIFO and SDRAM control IP core.

[0023] The digital radio frequency input signal is continuously written into the SDRAM write data FIFO.

[0024] The digital radio frequency output signal is continuously read from the SDRAM write data FIFO.

[0025] The delay control logic unit generates the address written from the SDRAM write data FIFO to the DDR3 SDRAM according to the set delay time parameter, and the address read from the DDR3 SDRAM to the SDRAM read data FIFO, the difference ...

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Abstract

The invention provides a pipelined digital radio frequency memory module. A delay control logic unit generates an address written from SDRAM write data FIFO to DDR3 SDRAM according to a set delay time parameter. The DDR3 SDRAM is read out to an address of SDRAM read data FIFO The difference between these two addresses equal to delay time divided by DDR3 SDRAM read and write clock cycles A control SDRAM controls IP to read a nuclear time sheet to read SDRAM write data FIFO data and writes into data of SDRAM read data FIFO. At the position of written labeling of SDRAM read data FIFO, the time sheet is distributed to read and write SDRAM writedata FIFO data. At the position of written emptiness of SDRAM read data FIFO, the time sheet is distributed to read and write SDRAM writedata FIFO data.

Description

technical field [0001] The invention relates to the field of radar echo signal generating equipment, which can be used in broadband radar echo signal generating equipment, and generates the same delay-adjustable echo signal for multiple radars that are turned on at the same time. Background technique [0002] The digital radio frequency memory DRFM is the main component of the active radar jammer in the modern electronic countermeasure system. It is used to accurately copy the received radar signal and then forward it to the radar system to generate a virtual target echo. DRFM technology can accurately reproduce radar signals, and has been widely used in various radar echo signal generation equipment. [0003] As the frequency storage bandwidth of the radar echo signal generation equipment continues to increase, the probability that there are multiple simultaneous start-up radars within the frequency storage bandwidth also increases. In some applications, it is necessary to ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16G01S7/35
CPCG06F13/1668G01S7/354
Inventor 沙文祥胥嘉佳
Owner NANJING GUORUI ANTAIXIN TECH
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