Motherboard and its internal memory apparatus

Abstract

The present invention relates to a memory device, which can be directly arranged on any motherboard in the prior art which can support the third-generation dual-channel synchronous dynamic random access memory DDR3 SDRAM, so as to integrate the advantages of the fly-by bus bracket and the T-shaped branch bracket, which are prepared in the JEDEC. Therefore, the memory device can improve the systemefficiency of the table computer in unit time.

Description

technical field [0001] The present invention relates to a motherboard of a desktop computer and its memory device, and in particular to a motherboard and its memory capable of handling relatively high-frequency work and improving the system performance per unit time of the desktop computer. device. Background technique [0002] Generally speaking, the motherboards of today's desktop computers are often equipped with memory slots for users to insert memory modules (DIMMs). Such a framework is formulated by the Joint Electron Device Engineering Council (JEDEC). [0003] It is worth mentioning that JEDEC has formulated some recommended reference design architectures for PCunbuffered DIMMs for desktop computers. Among them, when the memory chip on the above-mentioned unbuffered memory module is the second generation of Double Data Rate Two Synchronous Dynamic Random Access Memory (DDR2 SDRAM), JEDEC recommends that the T branch topology ) to design, and when the memory chip o...

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Problems solved by technology

[0009] However, under the fly-by bus architecture formulated by JEDEC, because the address line signal and command line signal sent by the memory controller 201 are sequentially transmitted from the memory chip DDR3 SDRAM0 to the memory chip DDR3 SDRAM7 in a serial manner, So it will cause a delay in signal transmission

Also because of this, each memory chip DDR3 SDRAM0~DDR3 SDRAM7 receives the address line signal and command line signal sent by the memory controller 201 and starts working at a different time point, so the memory controller 201 has to wait for a while The action of reading or writing data to the memory chips DDR3 SDRAM0~DDR3 SDRAM7 can be completed after a delay time, so the system performance per unit time of the desktop computer will be reduced

[0010] In addition, because the memory controller 201 has to wait for a period of delay before completing the action of reading or writing data to the memory chips DDR3 SDRAM0-DDR3 SDRAM7, the memory controller 201 must independently control each memory chip. DDR3 SDRAM0~DDR3 SDRAM7 can read or write data, so the design complexity of the memory controller 201 will increase a lot

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