Method for Forming Ferroelectric Memory Capacitor
a technology of ferroelectric memory and capacitor, which is applied in the field of ferroelectric memory capacitor formation, can solve the problem of higher leakage current through the ferroelectric capacitor than is desirabl
Inactive Publication Date: 2007-09-27
TEXAS INSTR INC
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Benefits of technology
The patent describes a method for making memory cells with a ferroelectric capacitor. The process involves creating a barrier layer, metal layers, and a hardmask layer on a dielectric layer. The hardmask layer is then patterned and used to etch the remaining layers using plasma processes at high temperatures. The resulting memory cell has sidewalls that form an angle with the surface of the dielectric layer. The technical effect of this method is to create a reliable and efficient memory cell with a high-quality ferroelectric capacitor.
Problems solved by technology
In addition the resulting leakage current through the ferroelectric capacitor is higher than desirable due to electrical shorts formed during the etching process.
Method used
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Embodiment Construction
[0011]FIG. 2(a) through FIG. 2(c) illustrate the fabrication of a ferroelectric memory capacitor according to an embodiment of the instant invention.
[0012] As shown in FIG. 2(a), a metal contact 80 is formed in a dielectric layer 70. In an embodiment of the instant invention the metal contact comprises tungsten, aluminum, or copper and contacts the source or drain of a MOS transistor not shown for clarity. The dielectric layer 70 comprises silicon dioxide, silicon oxide, PSG, BPSG, or any other suitable dielectric layer including low k spin-on-glass (SOG) dielectrics such as silsesquioxanes. In fabricating the ferroelectric memory capacitor according to an embodiment of the instant invention, a barrier layer 200 of titanium nitride or titanium aluminum nitride is first formed over the dielectric layer 70 and the contact 80. Following the formation of the barrier layer 200, a metal electrode layer 210 is formed over the barrier layer 200. The metal electrode layer 210 will form one ...
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Abstract
A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.
Description
[0001] This application is a divisional of application Ser. No. 10 / 610,498, filed Jun. 30, 2003, which claims the benefit of provisional Application No. 60 / 452,437, filed Mar. 6, 2003.CROSS-REFERENCE TO RELATED PATENT / PATENT APPLICATIONS [0002] The following commonly assigned patent / patent applications are hereby incorporated herein by reference: U.S. Pat. No. / Ser. No.Filing Date6,444,542Apr. 3, 20016,548,343Oct. 31, 2000FIELD OF THE INVENTION [0003] This invention relates generally to the field of electronic devices and more particularly to a method for forming a ferroelectric memory capacitor for integrated circuit applications BACKGROUND OF THE INVENTION [0004] High density integrated circuit memories have density dominated by cell size; thus alternative capacitor dielectrics such as high dielectric constant para-electrics for dynamic memory (DRAM) and ferroelectrics for nonvolatile ferroelectric memory (FeRAM) have received intense investigation. The para-electrics currently be...
Claims
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IPC IPC(8): H01L29/94H01L21/3065H01L21/02H01L21/311H01L21/3213H01L21/8246H01L27/105H10N97/00
CPCH01L21/31122H01L28/75H01L28/55H01L21/32136
InventorCELII, FRANCIS G.THAKRE, MAHESH J.SUMMERFELT, SCOTT R.
OwnerTEXAS INSTR INC