CMOS solid-state imaging device and method of manufacturing the same as well as drive method of CMOS solid-state imaging device
a solid-state imaging and imaging device technology, applied in semiconductor devices, diodes, electrical devices, etc., can solve the problems of difficult three-dimensional cover of the depth direction portion with a sufficient concentration, easy to cause thermal stress defects, and difficult to perform ion implantation
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first embodiment
[0038]FIG. 1 shows a CMOS solid-state imaging device according to the present invention. FIG. 1 shows a cross-sectional structure corresponding to the B-B line in the pixel region of FIG. 9.
[0039]In a CMOS solid-state imaging device 31 according to the first embodiment, a second conductive type, for example p-type, semiconductor well region 33 is formed in a first conductive type, for example n-type, silicon semiconductor substrate 32; a plurality of unit pixels 2 [2A, 2B, 2C and 2D], each of which includes a photodiode PD that is a photoelectric conversion portion and a plurality of MOS transistors, are formed in the p-type semiconductor well region 33; and an element isolation region 82, which is element isolation portion according to the present invention, (corresponding to the element isolation region 8 in FIG. 9) is formed between unit pixels 2 next to each other, and also within each unit pixel. In FIG. 1, in the p-type semiconductor well region 33 are formed: a photodiode PD ...
second embodiment
[0051]Next, FIG. 2 shows a CMOS solid-state imaging device according to the present invention. FIG. 2 shows the cross-sectional structure of the relevant part of a pixel region similar to the above described embodiment, and portions corresponding to those in FIG. 1 are given the same numerals and redundant explanations are omitted.
[0052]In a CMOS solid-state imaging device 51 according to the second embodiment, an element isolation region 83 (corresponding to the element isolation region 8 in FIG. 9) which isolates a floating diffusion (FD) and the other MOS transistor source drain region 49 from a photodiode PD of an adjacent pixel is formed of a first p-type isolation diffusion layer 43, a second p-type isolation diffusion layer 47 thereon, and an isolation oxide film 44 further thereon. The second isolation diffusion layer 47 is made to have impurity concentration equal to or higher than that of a p+ accumulation layer 39. With respect to other structures than that, detailed expl...
third embodiment
[0055]FIG. 3 shows a CMOS solid-state imaging device according to the present invention. FIG. 3 shows the cross-sectional structure of the relevant part of a pixel region similar to the above described embodiment, and portions corresponding to those in FIG. 1 are given the same numerals and redundant explanations are omitted.
[0056]In a CMOS solid-state imaging device 52 according to the third embodiment, an element isolation region 84 (corresponding to the element isolation region 8 in FIG. 8) formed of a p-type isolation diffusion layer 43 and an isolation oxide film 44 thereon is formed between a floating diffusion (FD) and the other MOS transistor source drain region 49 and a photodiode PD of an adjacent pixel.
[0057]In this embodiment, particularly in the case that the impurity concentration of the floating diffusion (FD) and the other MOS transistor source drain region 49 and the p-type isolation diffusion layer 43 of the element isolation region is high, a separation region 53 ...
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