Method for Operating a Non-Volatile Charge-Trapping Memory Device and Method for Determining Programming/Erase Conditions

a non-volatile charge and memory device technology, applied in the field of semiconductor processing and devices, can solve the problems of repetitive programming and erasing of cells, poor endurance, poor retention after cycling, etc., and achieve the effect of reducing power consumption and avoiding the increase of voltag

Inactive Publication Date: 2009-06-04
INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The method maintains a flat threshold voltage window without changes in spatial charge distribution, enhancing the endurance and retention characteristics of non-volatile memory devices by optimizing programming and erase conditions, reducing the need for voltage increases and power consumption.

Problems solved by technology

However, poor endurance and poor retention after cycling, i.e. repetitive programming and erasing of a cell, are major drawbacks of NROM™.

Method used

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  • Method for Operating a Non-Volatile Charge-Trapping Memory Device and Method for Determining Programming/Erase Conditions
  • Method for Operating a Non-Volatile Charge-Trapping Memory Device and Method for Determining Programming/Erase Conditions
  • Method for Operating a Non-Volatile Charge-Trapping Memory Device and Method for Determining Programming/Erase Conditions

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Embodiment Construction

[0036]As described with reference to FIG. 1-8, a set of programming and erase conditions for operating a semiconductor device, preferably a non-volatile memory device comprising a charge-trapping layer, is determined.

[0037]FIG. 1 shows a schematic cross-section of such a semiconductor device, namely a MOSFET-type device. This device (1) comprises a gate electrode (3) separated from the substrate (2) by a gate dielectric (4). Typically the gate electrode is formed from a semiconductor material such as polycrystalline silicon doped to obtain the desired workfunction and / or conductivity. This semiconductor material can be partially or fully silicided as known in the art or even metals, e.g. Al, TiN, TaN, are used. The gate dielectric (8) comprises a dielectric charge-trapping layer (10) such as silicon-nitride, silicon-rich oxide, silicon-oxynitride, an oxide layer comprising nanocrystals of a semiconductor material, e.g. polycrystalline silicon. Optionally this charge-trapping layer c...

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Abstract

A method for determining programming / erase conditions and a method for operating a charge-trapping semiconductor device are disclosed. Programming and erase conditions are determined such that a first net charge distribution variation profile, upon going from programmed to erased state, is substantially the opposite of a second net charge distribution variation profile, upon going from erased to programmed state.

Description

[0001]The present application claims the priority of European Patent Application No. EP 05109602.2 (filed Oct. 14, 2005), Provisional U.S. Application Nos. 60 / 704,859 (filed Aug. 1, 2005) and 60 / 687,076 (filed Jun. 3, 2005), and 11 / 446,538 (filed Jun. 2, 2006), and it incorporates these disclosures by reference.BACKGROUND[0002]1. Technical Field[0003]The present invention is in the field of semiconductor processing and devices, more specifically in the field of non-volatile charge-trapping memory devices. In particular, the present invention relates to a method for determining programming / erase conditions and a method for operating a non-volatile charge-trapping memory device.[0004]2. Background Art[0005]Non-volatile memories (NVM) are characterized by the fact that once a bit is stored in a memory cell this bit will be retained even when the memory cell is no longer powered. When electrical fields are used for erasing and programming of the memory cell, the NVM devices are also kno...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G11C16/06
CPCG11C16/04G11C16/0475G11C16/26G11C2029/5002G11C16/3495G11C29/50G11C16/349
InventorFURNEMONT, ARNAUD ADRIEN
OwnerINTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)