Semiconductor encapsulation structure by taking lead frame as substrate and applicable lead frame thereof

Abstract

The invention discloses a semiconductor encapsulation structure by taking a lead frame as a substrate and the applicable lead frame thereof. The semiconductor encapsulation structure mainly comprises at least one first pin, at least one second pin and a connecting strip which is arranged between the first pin and the second pin of the lead frame and also comprises a chip, two or more weld lines and an adhesive body which are arranged on the first pin, the second pin and the connecting strip, wherein the chip is provided with two or more weld pads, and the weld pads are connected to a first finger joint of the first pin and a second finger joint of the second pin by the weld lines; the connecting strip is provided with an extending part which exceeds the first finger joint of the first pinand the second finger joint of the second pin and is connected to the side of the adhesive body, and the extending part forms an arch for blocking stress transfer and preventing a crack being formed in such a way that drag stress is directly transferred in a bonded wafer area from the side of the adhesive body when the connecting strip is sheared, and the delamination of the connecting strip due to hydrosphere invasion along the crack of the connecting strip is avoided.

Description

technical field [0001] The present invention relates to a semiconductor device, in particular to a semiconductor package structure based on a leadframe and the applicable leadframe. Background technique [0002] Although in the field of semiconductor packaging, printed circuit boards or other substrates have gradually replaced lead frames as chip carriers, semiconductor package structures based on lead frames still have the advantages of low cost and high durability. One of the package structures is chip On the pin (COL, Chip-On-Lead), which is to set the semiconductor chip on a plurality of pins of the lead frame, use the bonding wire formed by the wire as the internal electrical connection between the chip and the pin, and pass The mold encapsulation enables the encapsulant to cover the chip and the bonding wire, and the exposed pins on the side of the encapsulant are used as external electrical connections. Although chip-on-lead (COL) semiconductor packaging construction...

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Problems solved by technology

[0004] However, if figure 1 As shown, the semiconductor package structure 100 is only carried on the first pins 110 on one side of the lead frame, and the length of the first pins 110 cannot be shortened, and the structural strength enough to carry the chip 140 cannot be provided.

During the potting process of forming the encapsulant 160 , the chip 140 is likely to be tilted or displaced due to mold flow pressure, which may even cause improper alignment of the first pins 110 , the chip 140 or the first bonding wires 151 Exposed, resulting in failure of semiconductor packaging products

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