Low-power consumption programmable frequency divider

Abstract

The invention relates to a low-power consumption programmable frequency divider. The low-power consumption programmable frequency divider is characterized by comprising N/N+1 dual-modulus preposed frequency divider circuits (1) and a programmable counter circuit (2) in communication with the N/N+1 dual-modulus preposed frequency divider circuits (1), wherein N is a natural number; the programmable counter circuit (2) comprises an asynchronous counter body circuit (21), a programmable counter control circuit (22), a swallow counter control circuit (23), a reset pulse generating circuit (24) and a counter output generating circuit (25); and the frequency of the programmable counter circuit (2) is input by the N/N+1 dual-modulus preposed frequency divider circuits (1). In the low-power consumption programmable frequency divider, a P-bit programmable counter and an S-bit programmable counter are integrated together and share one D trigger chain, so that the power consumption and the time delay are effectively reduced and the performance of the programmable frequency divider is improved.

Description

technical field [0001] The invention relates to a burr elimination programmable counter, which is mainly applied to a programmable frequency divider circuit in a radio frequency phase-locked loop. It has the characteristics of strong deburring ability, low power consumption, wide programmable range, simple structure and novel ideas. Background technique [0002] In the front-end circuit of the RF transceiver, the frequency synthesizer provides a stable and low-noise local oscillator signal for the up-mixing and down-mixing of the signal, and the signal transmission provides frequency band switching. RF phase-locked loop is an effective structure to realize frequency synthesizer. In the RF phase-locked loop circuit, the programmable frequency divider is the main module, which realizes the switching of the signal frequency band by controlling its own frequency division ratio. [0003] There are many ways to realize the programmable frequency divider, including two-frequency ...

AI Technical Summary

Problems solved by technology

The range of the frequency division ratio realized by the two-frequency cascaded programmable frequency divider is narrow, and it can only be an integer multiple of 2.

The biggest disadvantage of this kind of programmable frequency divider is that the P-bit programmable counter and the S-bit swallowing counter respectively require a counter main circuit composed of a cascaded D flip-flop, which brings a lot of delay to the circuit and relatively low power consumption. larger

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