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Arbitration circuit and its control method

An arbitration circuit and frequency limiting technology, applied in electrical digital data processing, instruments, etc., can solve problems such as bus use contention, bus control not being optimized, and cost increase, and achieve the effect of optimizing bus control

Inactive Publication Date: 2016-12-14
SONY SEMICON SOLUTIONS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, during the hardware development phase, no specific use case is established, making it often unclear what type of application will be executed
This makes it difficult to optimize the operation of the arbitration circuit used to perform bus control operations at the initial development stage
In addition, the optimal bus control may be different from one use case to another, thus there is a problem that after completing the hardware design of the arbitration circuit, it is found that the bus control has not been optimized and causes contention between bus usage
If any of these problems were present on any actual bus arbitration circuit, hardware reprogramming would have to be done adding cost

Method used

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  • Arbitration circuit and its control method
  • Arbitration circuit and its control method
  • Arbitration circuit and its control method

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0061] - Configuration of the bus control device

[0062] Now, refer to figure 1 , shows a schematic diagram illustrating an exemplary overall configuration of a bus control device practiced as the first embodiment of the present disclosure. The bus control device has M (M is an integer) masters 100 , slaves 200 , bus 300 and arbitration circuit 400 . The host 100 and the arbitration circuit 400 are connected to each other through a signal line 500 and a signal line 600 .

[0063] The signal line 500 is a signal line through which an arbitration request is transmitted from the host 100 to the arbitration circuit 400 . The signal line 600 is a signal line through which an arbitration result is transmitted from the arbitration circuit 400 to the host 100 . Arbitration here indicates that when the arbitration circuit 400 has received request signals from two or more hosts, the arbitration circuit 400 sends a grant signal to any one of these hosts. The request signal is a sign...

no. 3 example

[0148] - Configuration of the bus control device

[0149] The following reference Figure 20 to Figure 23 A third embodiment of the present disclosure is described. The arbitration circuit practiced as the first embodiment of the present disclosure selects a master by a priority method after band-pass processing. The arbitration circuit practiced as the third embodiment of the present disclosure is different from the arbitration of the first embodiment in that a master is selected by a priority scheme after band-pass processing and a longest elapsed time scheme.

[0150] refer to Figure 20 , shows a block diagram illustrating an exemplary configuration of an arbitration circuit 402 as an example of an arbitration circuit practiced as a third embodiment of the present disclosure. The arbitration circuit 402 is different from the arbitration circuit 400 practiced as the first embodiment in that a variable priority filter 445 is arranged instead of figure 2 Variable priorit...

no. 4 example

[0169] - Configuration of the bus control device

[0170] The following reference Figures 24 to 28 A fourth embodiment of the present disclosure is described. In the third embodiment described above, the arbitration circuit 402 grants within a certain clock cycle the request signal received in that clock cycle. The arbitration circuit 403 practiced as the fourth embodiment is different from the arbitration circuit 402 of the third embodiment in that a request signal received in a certain clock cycle is not granted in the clock cycle but granted in the next clock cycle.

[0171] refer to Figure 24 , shows a block diagram illustrating an exemplary configuration of an arbitration circuit 403 as one example of an arbitration circuit practiced as a fourth embodiment of the present disclosure. As described earlier, the arbitration circuit 402 of the third embodiment selects a request signal every clock cycle, and grants the selected request signal, thereby decrementing the numb...

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PUM

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Abstract

An arbitration circuit includes: a use frequency setting block configured to set, for each of a plurality of hosts, a set value for limiting a bus use frequency of each of the plurality of hosts; a use request management section configured to hold Each of the bus usage requests, and select unauthorized usage requests from the kept usage requests; the usage frequency restriction block is configured to limit the usage requests selected by the usage request management section to each of a plurality of hosts, so that multiple the bus usage frequency of each of the hosts will not exceed the set value set for each of the plurality of hosts; and a usage request authorization block configured to be among usage requests received from the plurality of hosts that is not restricted by the usage frequency limiting block , to authorize usage requests for any one of multiple hosts.

Description

technical field [0001] The present disclosure relates to an arbitration circuit, and more particularly to an arbitration circuit configured to optimize bus control between a master and a slave and a method of controlling the arbitration circuit. Background technique [0002] With complex and large-scale semiconductor integrated circuits based on design techniques such as SoC (System on Chip) for integrating various types of semiconductor chips into one chip, two or more devices can be connected to one device via a bus, These two or more devices are configured as control connected devices. In the following, the device to be controlled is called a slave, and the device controlling other devices is called a master. The host may include a CPU (Central Processing Unit), a DMAC (Direct Memory Access Controller), a GPU (Graphics Processing Unit), and the like. Slaves may include memory controllers, interface ports, video memory, and the like. [0003] In the case where there are...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/364
Inventor 加藤木聪
Owner SONY SEMICON SOLUTIONS CORP