LDPC (Low Density Parity Check) encoder

An encoder and codeword technology, applied in the field of communication, can solve the problems such as the LDPC encoder implementation method is not given, so as to improve data processing speed and throughput, high encoding efficiency, and meet the requirements of high-speed digital information transmission Effect

Inactive Publication Date: 2012-09-19
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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Problems solved by technology

[0003] In the TV broadcast communication protocol of DVB-T2, only the code length and code rate of the code word

Method used

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  • LDPC (Low Density Parity Check) encoder

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[0032] The LDPC encoder of the present invention supports two code lengths of 16200bit and 64800bit, 1 / 5, 4 / 9, 3 / 5, 2 / 3, 11 / 15, 7 / 9, 37 / 45, 1 / 2, 3 / 4, Eleven bit rates, 4 / 5 and 5 / 6; each I / 0 interface outputs a group of information bits with a bit width M=360bit; the shift step q can be obtained by checking the following table:

[0033]

[0034]

[0035] Such as figure 1 As shown, the LDPC encoder includes I / O interface, RAM address and shift factor generation module, RAM update calculation module, S matrix generation module, S matrix column and calculation module, check digit generation module, and code word generation module; The S matrix generating module includes a RAM for storing each element of the S matrix; the RAM is designed according to a bit width of 360 bit, and stores nk S matrix elements;

[0036] The I / O interface is used to output a group of information bits with a bit width of 360 each time;

[0037] The RAM address and shift factor generation module is used to, dur...

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Abstract

The invention provides an LDPC (Low Density Parity Check) encoder. When the LDPC encoder generates an S matrix, a parallel calculation method is adopted; and elements of one row of the S matrix are updated by using one group of information bits output by an RAM (Random Access Memory) updating and calculating module. When the sum of an S matrix array is calculated, the manner that after the S matrix is completely generated, each row of the elements of the S matrix are subjected to XOR is not adopted; the information bits output by the RAM updating and calculating module is directly calculated to obtain an S matrix array sum, and the result of the S matrix array sum and an S matrix array generating result are obtained at the same time, so as to shorten the generation time of a checking bit. Furthermore, the RAM updating and calculating module only circulates and displaces toward one right direction in an encoding process; an RAM address and displacement factor generation module is used for sequencing an RAM address for reading and writing from a sequence from small to big according to a corresponding displacement value, and the displacement value is sequentially output to the RAM updating and calculating module for circulating and displacing, so that the complexity of displacement is reduced and the encoding time is further shortened.

Description

technical field [0001] The present invention relates to communication technology, in particular to Low Density Parity Check Code (LDPC, Low Density Parity Check) coding technology. Background technique [0002] In the TV broadcast communication protocol of the second-generation European digital terrestrial TV broadcast transmission standard DVB-T2 formulated by the European Telecommunications Standards Institute ETSI, the LDPC forward error correction coder is applied in the forward error correction FEC part of the channel coding . [0003] In the TV broadcast communication protocol of DVB-T2, only two parts of information, the code length and code rate of the code word and the parity check matrix, are given, and the specific implementation method of the LDPC encoder is not given. [0004] The LDPC check matrix structure is sparse, and the LDPC code directly uses the check matrix for encoding. The structure of check matrix H is as follows: [0005] [0006] Check matri...

Claims

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Application Information

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IPC IPC(8): H03M13/11
Inventor 林水生李广军马超伍国铜
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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