Instruction pre-send method and device, instruction management system, computing core

Abstract

Disclosed are a method and a device for instruction presending, an instruction management system and an operation core. The method for instruction presending includes dividing a program into instruction blocks according to an execution sequence of the program, setting an instruction superblock list of the instruction blocks, and sending the instruction blocks to at least one operation core according to the execution sequence. The instruction superblock list includes identifiers of the instruction blocks, storage addresses of the instruction blocks and identifiers of next instruction blocks. According to the technical scheme, instruction off-target and waiting delay of the operation cores can be reduced effectively and operation efficiency of the operation core is improved.

Description

technical field [0001] The invention relates to the technical field of command management, in particular to a command pre-send method and device, a command management system and a computing core. Background technique [0002] In a general-purpose processor, a hierarchical instruction storage structure is generally adopted, that is, instructions are stored in storage media of different levels. The computing core (the component device of the processor, each computing core can be regarded as a small processor) obtains instructions from the local memory at runtime. Due to the limited local memory capacity of the computing core, it is easy to fail to fetch instructions. That is to say, if the operation core does not store the instruction to be executed, the operation core needs to obtain the instruction from the upper-level instruction memory before continuing to run. Failure to fetch instructions is also called instruction miss. In the case of a hierarchical instruction storage...

AI Technical Summary

Problems solved by technology

[0011] However, SIMD technology requires each instruction of each computing core to be executed synchronously, and the resources of the computing core are usually difficult to be fully utilized, and the computing power of all computing cores cannot be utilized, which limits the scope of application of the technology.

[0012] In multi-core and many-core processors, as the number of computing cores increases, the memory capacity in the computing cores is small. If the SPMD program size is greater than the memory capacity in the computing cores, frequent instruction fetching operations will still occur if the instruction fetch misses the target. Operational conflicts are intensified, communication network congestion is serious, and the waiting time for fetching instructions of the computing core is longer, which has a great impact on the computing efficiency of the computing core

Therefore, in multi-core and many-core processors, the memory capacity in the computing core limits the scope of application of SPMD technology

[0013] The method in the Chinese patent with publication number CN1466716A can only provide instruction prefetch service for one processor, and is not suitable for the processor structure of multi-core and many-core processors

On the other hand, the method for prefetching instructions in this patent requires an additional auxiliary processor for each computing core to execute a simplified version of the program, and the hardware overhead is large

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