The invention relates to a multi-core satellite-bone computer, belonging to the data processing technical field of aerospace and aiming at solving the problem of slow processing speed of the satellite-bone computer by adopting an ASIC software realization mode. The satellite-bone computer comprises an FPGA based on an SRAM, n PROMS, n SRAMS, an anti-fuse FPGA and a configuration NOR type flash memory, wherein the FPGA based on the SRAM forms a multi-core structure with n processors, the anti-fuse FPGA comprises a read-back brush write interface circuit, a monitoring circuit and a control circuit, the monitoring circuit monitors the health state of the n processors, if an abnormal part needs reconstruction, the read-back brush write interface circuit reads the configuration file of the FPGA based on the SRAM at set speed, compares the configuration file of the FPGA with an original configuration file, and reconstructs the error parts if different. The multi-core satellite-bone computer can realize automatic switching system function by FPGA hardware programming according to satellite missions.