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Package and manufacturing method thereof

An encapsulation and encapsulation layer technology, which is used in semiconductor/solid-state device manufacturing, electrical components, and electrical solid-state devices, etc., can solve the problems of signal integrity and signal area degradation and cannot be effectively dispersed, and improve signal integrity. performance, good electrical performance, and the effect of expanding the area

Active Publication Date: 2016-08-10
SAMSUNG SEMICON CHINA RES & DEV +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, because in the existing package structure, the semiconductor chip is located on the substrate and encapsulated by the encapsulation layer, it may not be possible to effectively dissipate the heat generated by the operation of the semiconductor chip.
[0005] In addition, in the package structure of the prior art, the ground terminal of the semiconductor chip is electrically interconnected with the substrate through bonding wires like other input / output terminals of the semiconductor chip, so when the semiconductor chip operates with high-frequency signals, the signal Integrity may be degraded due to the small area of ​​the ground signal area

Method used

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  • Package and manufacturing method thereof
  • Package and manufacturing method thereof

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Embodiment Construction

[0023] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the exemplary embodiments of the present invention can be implemented in many different forms and should not be limited to the examples set forth herein. On the contrary, these examples are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0024] figure 1 It is a cross-sectional view showing the package 10 according to an exemplary embodiment of the present invention. in figure 1 A package 10 according to an exemplary embodiment of the present invention is shown taking a ball grid array (BGA) package as an example. However, the exemplary embodiments of the present invention are not limited thereto, and those skilled in the art can adopt various suitable packaging forms to implement the present invention.

[0025] Such as figure 1 As ...

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Abstract

The invention provides a package and a manufacturing method thereof. The package includes: a substrate; a semiconductor chip mounted on an upper surface of the substrate, the semiconductor chip including a ground terminal located in a middle area of ​​the upper surface of the semiconductor chip and an input / output located in an edge area of ​​the upper surface of the semiconductor chip terminal, the input / output terminal is electrically connected to the substrate; the encapsulation layer is formed on the edge area of ​​the upper surface of the substrate and the semiconductor chip with the input / output terminal to encapsulate the semiconductor chip, the encapsulation layer has an upper surface that exposes the semiconductor chip A groove in the middle region having a ground terminal; a conductive layer formed in the groove of the encapsulation layer and electrically connected to the ground terminal. The package can have good electrical performance and heat dissipation performance.

Description

Technical field [0001] The invention relates to a package and a manufacturing method thereof. Background technique [0002] With the continuous deepening of semiconductor chip packaging technology and product diversification needs, high speed, low cost, small size, and excellent electrical performance are its important development trends. Especially under the high frequency requirements, the electrical performance and heat dissipation Increasingly demanding. [0003] The existing package structure is a single-layer board, a double-layer board or a multi-layer board structure, which usually consists of a substrate, a semiconductor chip mounted on the substrate, and bonding (metal) leads that realize electrical interconnection between the substrate and the semiconductor chip. It is composed of an adhesive layer for bonding and fixing the semiconductor chip on the substrate, and an encapsulating layer that encapsulates and protects the semiconductor chip and the electrical interconne...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488H01L21/60H01L23/373
CPCH01L24/97H01L2224/48091
Inventor 马慧舒
Owner SAMSUNG SEMICON CHINA RES & DEV
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