Clock and data recovery circuit and clock and data recovery method

Abstract

The invention discloses a clock and data recovery circuit and a clock and data recovery method. The clock and data recovery circuit comprises a clock generation module, a clock selection module, a phase discriminator and a digital correlation processing module, wherein the clock generation module is used for receiving input clock signals, generating multi-channel clock signals identical in frequency and different in phase and sending the multi-channel clock signals to the clock selection module; the clock selection module is used for selecting continuous multi-channel clock signals from the multi-channel clock signals identical in frequency and different in phase to the phase discriminator and selecting one-channel clock signal serving as a data lock to the digital correlation processing module; the phase discriminator is used for receiving input data, oversampling the input data according to multi-channel oversampling clocks and sending the oversampled data to the digital correlation processing module; the digital correlation processing module is used for processing the oversampled data, recovering the data and feeding back one clock selection signal to the clock selection module; according to the feedback clock selection signal, the clock selection module selects and outputs the clock signals as same as the recovered data in phase. The clock and data recovery circuit has he advantages of simple structure, short locking time, small recovered clock jitter and the like.

Description

technical field [0001] The invention relates to the technical field of digital communication, in particular to a clock data recovery circuit and a clock data recovery method. Background technique [0002] The clock data recovery circuit is the core module of the high-speed transceiver, and the high-speed transceiver is an important part of the communication system. When the data stream is transmitted in the serial data line, there is no clock signal attached, and the serial data receiving end needs to pass the clock data recovery circuit CDR (Clock and Data Recovery) from the received digital signal containing large interference and jitter The synchronous clock is extracted, and the data signal is re-sampled by the synchronous clock to obtain stable and reliable data. figure 1 is the schematic diagram of the clock data recovery circuit, as figure 1 As shown, there are two basic goals in designing a clock data recovery circuit, one is to recover the clock of the original da...

AI Technical Summary

Problems solved by technology

[0003] The invention provides a clock data recovery circuit and a clock data recovery method to solve the defects of the existing clock data recovery schemes such as large jitter of the recovered clock and long locking time.

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