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Method for patterning integrated circuits

A technology of integrated circuits and target patterns, which is applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., and can solve problems such as increasing the complexity of processing and manufacturing ICs

Active Publication Date: 2018-02-27
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This scaling down also increases the complexity of processing and manufacturing ICs, and similar developments in IC processes and manufacturing are required to enable these advances

Method used

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  • Method for patterning integrated circuits
  • Method for patterning integrated circuits
  • Method for patterning integrated circuits

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Embodiment Construction

[0027] The following disclosure presents a number of different embodiments, or examples, for implementing the different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are of course merely examples and are not intended to be limiting. Additionally, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the purposes of brevity and clarity, and does not in itself dictate a relationship between the various embodiments and / or configurations described. In addition, performing the first process before the second process in the specification may include an embodiment in which the second process is directly performed after the first process, and may also include an embodiment in which an additional process may be performed between the first and second processes. example. Various features may be arbitrarily drawn in different scales fo...

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Abstract

A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The method further includes removing at least a portion of the spacer layer to expose the plurality of lines and the substrate. The method further includes shrinking the spacer layer disposed onto the sidewalls of the plurality of lines and removing the plurality of lines thereby resulting in a patterned spacer layer over the substrate.

Description

technical field [0001] The present invention relates to methods for patterning integrated circuits. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation of ICs. During the evolution of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component that can be produced using a fabrication process (or Wire)). This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing ICs, and similar developments in IC processes and manufacturing are required to achieve these advances. Contents of the invention [0003] In order to solve the pr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/027H01L21/768
Inventor 童思频黄鸿仪杨能杰谢静华
Owner TAIWAN SEMICON MFG CO LTD