Virtual physical address conversion system and its management method

Abstract

The invention discloses a system for virtual-to-physical address transition and a management method of the system. The management method of the system for the virtual-to-physical address transition comprises the following steps: providing a first memory space, wherein the first memory space comprises a plurality of buffer entries; providing a second memory space, wherein the second memory space comprises a plurality of transition entries, and the transition entries correspond to a plurality of transition indexes; when a writing instruction is received, first virtual-to-physical address transition is written into a specific buffer entry of the buffer entries, according to the position of a first part of a first virtual address corresponding to the first virtual-to-physical address transition, memorizing the first virtual-to-physical address transition in a writing transition entry of the transition entries, and memorizing the first virtual address and a writing transition index corresponding to the writing transition entry into the specific buffer entry.

Description

technical field [0001] The present invention relates to memory management, in particular to a virtual physical address translation system management method and a related virtual physical address translation system using a part of a virtual address as an index. Background technique [0002] The memory management unit (memory management unit) improves the query efficiency of the page table (page table) through the translation lookaside buffer (TLB). For example, a translation lookaside buffer used by a microprocessor without interlocked pipeline stages (MIPS) may have multiple (eg, 64) entries for high-speed lookup, each of which Each entry can store a virtual-to-physical address translation between a virtual address and a physical address. [0003] However, when looking up in the translation lookaside buffer, it is necessary to map a virtual address to be looked up with a virtual address stored in each entry (that is, fully-associative mapping). That is to say, multiple (fo...

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Problems solved by technology

[0003] However, when looking up in the translation lookaside buffer, it is necessary to map a virtual address to be looked up with a virtual address stored in each entry (that is, fully-associative mapping). That is to say, multiple (for example, 64) comparison circuits are required. Therefore, if the number of conversion lookaside buffer entries is increased to improve system efficiency, the circuit area of ​​the conversion lookaside buffer will increase accordingly, and the processing speed will also decrease. , however, if the number of translation lookaside buffer entries is reduced, system efficiency will be reduced (for example, the probability of translation lookaside buffer loss (TLB miss) will increase)

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