Method and system for orderly storing CPLD data packets

Abstract

The invention relates to a method and system for orderly storing CPLD (Completion Data) data packets. The method comprises the following steps of segmenting DMA (Direct Memory Access) reading requests sent by PCI (Peripheral Component Interconnect) Express endpoint equipment to a host memory into a plurality of sub DMA reading requests with continuous labels by using a label order issuing system, and sending the plurality of sub DMA reading requests to a host; receiving CPLD data packets returned by the host, and determining storage base addresses of the CPLD data packets in the PCI Express endpoint equipment according to labels of the CPLD data packets; performing offset address calculation on the CPLD data packets with same labels, and determining offset addresses of the CPLD data packets; and storing the corresponding CPLD data packets according to the determined offset addresses and the base addresses of the CPLD data packets in the PCI Express endpoint equipment. The method and the system have the advantages that the label order issuing system is built; the large-data-volume DMA reading operation is realized; a base address and offset address calculation system is built; the high-speed reading scheme of the PCI Express endpoint equipment and the efficient high-speed and undelayed storage scheme of CPLD data in an RAM (Random Access Memory) are realized; and the data throughput rate is greatly improved.

Description

technical field [0001] The invention relates to the field of data storage based on the PCIExpress high-speed bus, in particular to a method and system for orderly storing CPLD (CompletionData) data packets returned by a PCIExpress endpoint device initiating a DMA read request to a host memory. Background technique [0002] The first-generation I / O buses include ISA, EISA, VESA, and MicroChannel (MicroChannel) buses, while the second-generation I / O buses include PCI, AGP, and PCI-X. PCIExpress is a third-generation high-performance I / O bus used to interconnect peripheral devices such as computing and communication platform applications. [0003] The I / O bus of the first two generations was a parallel bus, and multiple devices shared a bus. The third-generation bus PCIExpress inherits the most useful features of the second-generation bus architecture, and adopts new research results in computer architecture. It can realize serial and point-to-point communication between two d...

AI Technical Summary

Problems solved by technology

However, there is a limitation in the PCIExpress specification. The maximum data transfer volume allowed by a DMA read request cannot exceed MaxRequestSize, and MaxRequestSize is generally 512 in PCIExpress endpoint devices, and the maximum cannot exceed 4096 bytes.

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