Pixel drive circuit, display substrate and display device

Abstract

The invention relates to a pixel drive circuit, comprising a signal output transistor and other transistors, wherein the width of a source electrode of the signal output transistor is less than those of source electrodes of the other transistors; the width of a drain electrode of the signal output transistor is greater than those of drain electrodes of the other transistors. According to a technical scheme provided by the invention, by reducing the width of the source electrode of the signal output transistor, the opposite areas of the source electrode and the drain electrode can be reduced, so that the gate source capacitance of the signal output transistor can be reduced. On the other hand, by increasing the width of the drain electrode of the signal output transistor, the gate-drain capacitance of the signal output transistor is increased, and then the coupling voltage is enabled to be reduced. Larger coupling voltage generated at a grid electrode of the signal output transistor is avoided, and a high temperature AD problem of the signal output transistor is improved.

Description

technical field [0001] The present invention relates to the field of display technology, in particular, to a pixel driving circuit, a display substrate and a display device. Background technique [0002] GOA (Gate on Array) technology can effectively improve the integration of the pixel driving circuit. One of the pixel driving circuits outputs the clock signal through the signal output transistor. The source of the signal output transistor is connected to the clock signal terminal. When the gate is input with high level , the clock signal can be derived through the drain. That is, in a normal working state, when a high level is input to the gate of the signal output transistor, the signal output transistor can be turned on, thereby outputting the clock signal through the drain. [0003] However, when the gate of the signal output transistor is input with a low level, due to the existence of coupling capacitance in the pixel drive circuit, the high level signal at the clock...

AI Technical Summary

Problems solved by technology

[0003] However, when the gate of the signal output transistor is input with a low level, due to the existence of coupling capacitance in the pixel drive circuit, the high level signal at the clock signal terminal will affect the gate of the signal output transistor, forming a coupling at the gate of the signal output transistor. Voltage

Especially under high temperature working conditions, the Vth (threshold voltage) of the signal output transistor will drift, so that the signal output transistor can be turned on when the gate voltage is small, causing the gate of the signal output transistor to be affected by the high level of the clock signal It is more serious, so that high temperature AD (Abnormal Display, poor display) occurs when the gate of the signal output transistor is input at a low level.

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