Superjunction device and method of manufacturing the same

Abstract

The present invention discloses a super junction device. P-type columns of at least one super junction unit are internally provided with N-type electric field barrier layers, and the N-type electric field barrier layers are configured to segment the P-type columns into first and second P-type columns which are respectively located at the top portions and the bottom portions of the electric field barrier layers; the N-type electric field barrier layers are configured to realize segmentation exhaustion of super junction structures at a top portion and a bottom portion; when a source-drain voltage of a super junction device is smaller than or equal to a first voltage value, the super junction structure at the top portion is only exhausted; and when the source-drain voltage of the super junction device is larger than the first voltage value, the super junction structures at the top portion and the bottom portion are exhausted. The present invention further discloses a manufacturing methodof a super junction device. According to the invention, a gate-drain capacitance and the minimum value of the gate-drain capacitance can be improved to effectively reduce the electromagnetic interference performance of the device in an application circuit and effectively reduce current and voltage overshoot caused by the device in the application circuit, reversely recovered soft factors of the device can be increased, and a breakdown voltage of the device can be maintained.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor integrated circuits, in particular to a super junction device; the invention also relates to a method for manufacturing the super junction device. Background technique [0002] The super junction structure is composed of alternately arranged N-type pillars and P-type pillars. If the superjunction structure is used to replace the N-type drift region in the vertical double-diffused MOS transistor (Vertical Double-diffused Metal-Oxide-Semiconductor, VDMOS) device, the conduction path is provided through the N-type column in the conduction state, and when the conduction The P-type column does not provide a conduction path; in the off state, the PN column jointly bears the reverse bias voltage, forming a super-junction metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). The super-junction MOSFET can greatly reduce the on-resistance o...

AI Technical Summary

Problems solved by technology

However, in the existing structure, the carriers in the N-P column are completely exhausted when Vds is less than 50V, so even if the operating voltage Vdd is as small as 200V V to 300V, the remaining carriers after the device voltage reaches Vdd are only N-P part of the carriers in the part of the N-type buffer layer 30 under the pillars, so that the softness factor of the device body diode in reverse recovery cannot be improved

Images