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clock generation circuit

A clock generation circuit and clock technology, applied in the direction of electric pulse generator circuit, etc., can solve the problem of low frequency precision of clock signal and so on

Active Publication Date: 2018-01-26
SPREADTRUM COMM (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The problem solved by the present invention is that the frequency accuracy of the clock signal generated by the existing clock generation circuit is low

Method used

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Embodiment Construction

[0023] In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0024] Such as figure 2 As shown, the embodiment of the present invention provides a clock generating circuit suitable for outputting a target clock signal. The clock generation circuit includes:

[0025] A self-oscillating clock generating unit 1, adapted to generate a self-oscillating clock signal;

[0026] The sampling unit 2 is adapted to use a reference clock signal to sample the self-oscillating clock signal, so as to obtain the number N of cycles of the reference clock signal included in the M cycles of the self-oscillating clock signal, and the reference clock signal The frequency is greater than the frequency of the self-oscillating clock signal;

[0027] Calculation unit 3, adapted to obtain the frequency division coefficient...

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Abstract

A clock generating circuit, adapted to output a target clock signal, comprising: a self-oscillating clock generating unit, adapted to generate a self-oscillating clock signal; a sampling unit, adapted to use a reference clock signal to sample the self-oscillating clock signal, to obtain The cycle number N of the reference clock signal contained in the M cycles of the self-oscillating clock signal, the frequency of the reference clock signal is greater than the frequency of the self-oscillating clock signal; the calculation unit is adapted to obtain the frequency division factor Fref is the frequency of the reference clock signal, and Ftag is the frequency of the target clock signal; a frequency divider is adapted to perform frequency division processing on the self-oscillating clock signal based on the frequency division factor divider to obtain the target clock Signal.

Description

technical field [0001] The invention relates to a clock generating circuit. Background technique [0002] In the existing clock signal generation circuit, the general low-cost self-oscillating circuit itself is very inaccurate, and there may be as much as 20% frequency error in terms of its frequency. [0003] figure 1 The invention is an existing self-oscillating clock generating circuit. The self-oscillating clock generating circuit includes: an AND gate 11 and an odd number of inverters 12 . [0004] The odd number of inverters are connected in series, the output end of the AND gate 11 is connected to the first inverter 12 in series, and the output end of the last inverter 12 in series is connected to an input end of the AND gate 11, The other input terminal of the AND gate 11 inputs an enable signal EN. [0005] The enabling signal can trigger the self-oscillating clock generation circuit to work, so as to output the self-oscillating clock signal. Although this circ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K3/02
Inventor 江正忠杜禾
Owner SPREADTRUM COMM (SHANGHAI) CO LTD