Extensible pipelined circuit aiming at SM4 cryptographic algorithm and implementation method thereof
A cryptographic algorithm and pipeline technology, which is applied in the field of scalable pipeline circuits and its realization, can solve problems such as low throughput rate, not allowing new data to be loaded, and large area overhead
Patent Information
- Authority / Receiving Office
- CN · China
- Current Assignee / Owner
- Publication Date
- 2016-05-11
Smart Images
Figure 1 Figure 2 Figure 3
Abstract
Description
Technical field:
[0001] The invention relates to the fields of information security technology and integrated circuit design, in particular to an extensible pipeline circuit for SM4 encryption algorithm and its realization method. Background technique:
[0002] The SM4 algorithm, the original SMS4 algorithm, is a block symmetric cipher algorithm for wireless LAN products announced by the State Commercial Encryption Administration Office in January 2006, and was approved as an industry standard by the State Encryption Administration in March 2012.
[0003] The SM4 algorithm is a block cipher algorithm, and its block length and key length are both 128 bits. In the SM4 algorithm standard, the algorithm is divided into three parts: encryption algorithm, decryption algorithm and key expansion algorithm. The encryption algorithm consists of 32 iterative operations and 1 reverse sequence transformation. Each iterative operation needs to load a set of round keys into the round func...
Examples
Embodiment Construction
[0018] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.
[0019] The present invention provides a kind of extensible pipeline circuit aimed at SM4 cryptographic algorithm, such as figure 1 As shown, it specifically includes: an input data buffer module S101, a data distribution and enable signal generation module S102, a control state machine S103, an SM4 algorithm core array S104, and an output data buffer S105. Among them, the input data buffer module S101 splices the continuously input N (N is equal to 8, 16, 32, 64) bit data into 128-bit data after 128 / N cycles; the data distribution and enable signal generation module S102 will input The 128-bit data output by the buffer is allocated to each SM4 algorithm core in turn, and provides an enable signal for each SM4 algorithm co...