Extensible pipelined circuit aiming at SM4 cryptographic algorithm and implementation method thereof

Abstract

The invention discloses an extensible pipelined circuit aiming at an SM4 cryptographic algorithm and an implementation method thereof. According to the invention, an encryption and decryption iterative operation and a key extending algorithm are implemented through an SM4 algorithm core array, the SM4 algorithm core array comprises N / 4 SM4 algorithm cores, each SM4 algorithm core performs loop iteration 32 times to finish encryption / decryption of 128 bits of data, the N / 4 SM4 algorithm cores perform parallel execution, the number of the SM4 algorithm cores is regulated according to I / O bit width, and given that the I / O bit width is N, so the number of the algorithm cores in the structure is N / 4. According to the invention, encryption / decryption of the SM4 algorithm can be executed in a pipelined form, and a circuit structure can be regulated according to I / O interfaces with different bit widths.

Description

Technical field: [0001] The invention relates to the fields of information security technology and integrated circuit design, in particular to an extensible pipeline circuit for SM4 encryption algorithm and its realization method. Background technique: [0002] The SM4 algorithm, the original SMS4 algorithm, is a block symmetric cipher algorithm for wireless LAN products announced by the State Commercial Encryption Administration Office in January 2006, and was approved as an industry standard by the State Encryption Administration in March 2012. [0003] The SM4 algorithm is a block cipher algorithm, and its block length and key length are both 128 bits. In the SM4 algorithm standard, the algorithm is divided into three parts: encryption algorithm, decryption algorithm and key expansion algorithm. The encryption algorithm consists of 32 iterative operations and 1 reverse sequence transformation. Each iterative operation needs to load a set of round keys into the round func...

AI Technical Summary

Problems solved by technology

The existing hardware circuit structure mostly uses a loop to achieve 32 iterations, that is, a set of 128-bit data is not allowed to load new data before 32 iterations are completed, which leads to low throughput

However, if the 32 iterations are fully expanded, although a high throughput rate can be obtained, it will bring a large area overhead

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