12 results about "128-bit" patented technology

The application provides a splitting implementation method of a RISC-V vector cryptography instruction, which splits a message scheduling instruction into a plurality of micro-instructions for execution on a processor with a vector data path bit width of 128 bits according to a preset splitting rule in an instruction decoding stage, the splitting rule comprising: obtaining a message scheduling instruction in a SHA-512 algorithm, the message scheduling instruction being used to expand an input message block into a required message sequence; splitting the message scheduling instruction into a 0th type micro-instruction for processing a transformation path of sig0 and a 1st type micro-instruction for processing a transformation path of sig1 according to a calculation type; and the method does not introduce additional storage data space, and can reduce the area overhead of the processor for implementing the instruction while maintaining the unit data path operation throughput.

A method for forwarding a packet is disclosed. The method comprises: receiving the packet, wherein a first packet header of the packet comprises a segment list for forwarding the packet, the segment list comprises a plurality of identifiers arranged in sequence, each of the plurality of identifiers corresponds to a network device or a link, the list comprises a first element with a length of 128 bits, the first element comprises at least two adjacent identifiers of the plurality of identifiers, and the first packet comprises a first pointer; determining a position of a first identifier in the first element according to a value of the first pointer, the first identifier is one of the at least two adjacent identifiers; copying at least one identifier starting from the first identifier to a second packet header of the first packet to generate a second packet; and sending the second packet. By the method, the length of the segment list can be reduced, and the efficiency of packet transmission can be improved.

The application discloses an automobile remote control key encryption method based on an AES algorithm, and relates to the technical field of intelligent automobiles, and comprises the following steps: obtaining manufacturer information, wherein the manufacturer information is a manufacturer authentication certificate and a manufacturer code set by a manufacturer; generating a serial number, wherein the serial number is divided into multiple plaintext blocks, and a first encrypted information is preliminarily encrypted by combining the multiple plaintext blocks with the manufacturer information; the first encrypted information is 108 bits; the first encrypted information is subjected to a bit complement encryption to generate second encrypted information, the serial number is combined with the manufacturer code to form the first encrypted information, the first encrypted information is complemented to 128 bits, the same manufacturer can encrypt different ciphertexts, and the third encrypted information is generated by combining a ciphertext stream and a key stream, so that the generation and combination of the third encrypted information can also not be according to fixed bits, the combination mode is more flexible, and statistical analysis attacks are effectively prevented.

The invention provides a simd-based floating point transpose logic implementation method, which comprises the following steps of: S1, respectively reading four rows of data of a matrix A by using an mx512laq2w instruction, respectively storing the four rows of data into an I0 register, an I1 register, an I2 register and an I3 register, and simultaneously reserving a space with the same size as the previous element behind each element for splicing operation; the method comprises the following steps: S1, respectively storing 64-bit low-order 32-bit data of an I1 register into 64-bit middle-high-order 32-bit data of an I0 register by using two ilvew instructions, and storing 64-bit low-order 32-bit data of an I3 register into 64-bit middle-high-order 32-bit data of an I2 register, and S3, respectively storing ab and cd at adjacent positions of the registers and storing a1b1 and c1d1 at adjacent positions of the registers for the I0 register and the I2 register by using an ilved instruction and an ilvod instruction; and S4, by using four data storage instructions saq instructions, storing front 128 bit data of the register I1 into the first row of the matrix A1, storing rear 128 bit data of the register I1 into the third row of the matrix A1, storing front 128 bit data of the register I1 into the second row of the matrix A1, and storing rear 128 bit data of the register I1 into the fourth row of the matrix A1 to obtain a matrix A transposed matrix A1.

The invention discloses a segment identifier compression method oriented to a satellite network, which aims at the problem of high SRH head overhead caused by a relatively long path, and is characterized in that a 128-bit SID is compressed into a 32-bit C-SID in combination with satellite network topology position information, and the head length is reduced while segment routing semantics and programmable capability are maintained; one SID or 1-4 C-SIDs are loaded in a 128-bit segment identifier packaging unit carrier of the SRH, the C-SID, the SID and a filling unit are distinguished through CSI and C-Flag, and a segment list is traversed in combination with a segment index SL, so that unified identification and processing of the SID and the C-SID are realized; after the current C-SID takes effect, decoding the current C-SID to generate an IPv6 destination address for forwarding; according to the method, the SRv6 control plane protocol and the SRH fixed head format do not need to be modified, the SRH head overhead in the satellite network can be reduced, and the method is suitable for SRv6 service bearing in the satellite network.

The embodiment of the present application provides a time delay reporting method, which comprises the following steps: reporting target time delays corresponding to data in multiple specific positions in a data stream, wherein the multiple specific positions are spaced apart by a fixed length; wherein: the period of the multiple specific positions corresponds to the length of one or more convolution interleaving sequences, the specific positions correspond to delay lines with the maximum or minimum introduced time delay in the convolution interleaving; or, the period of the multiple specific positions corresponds to the length of one or more distribution sequences, each of the distribution sequences corresponds to eight sub-sequences after distribution; or, the period of the multiple specific positions corresponds to an integer multiple of N data blocks, each of the N data blocks corresponds to a forward error correction (FEC) code word, N is a positive integer, and the length of each data block is: 120 bits, or 128 bits, or 110 bits, or 126 bits. According to the scheme, time delay can be accurately reported.

The application discloses a lightweight encryption method and device based on an ARX module. The method comprises the following steps: storing a master key in a linear feedback shift register (LFSR); taking four beats of LFSR precession as one round and generating a sub-key; generating 32 sub-keys in sequence to form a sub-key sequence; obtaining plaintext to be encrypted, and grouping the plaintext to be encrypted; performing 32 rounds of encryption on each group of plaintext based on the sub-key sequence; merging the encrypted ciphertext of each group of plaintext to obtain the overall encrypted ciphertext corresponding to the plaintext to be encrypted; and obtaining the overall encrypted ciphertext by a decryption party, grouping the overall encrypted ciphertext, and taking each group to include 128 bits; and performing a decryption operation on each group of ciphertext based on the sub-key sequence. The application can meet the high efficiency in the resource-limited scene, and can resist the security threats caused by differential analysis and linear analysis.

The invention discloses a lightweight segmented routing optimization method applied to a spaceborne router. The method comprises the following steps: a source node is a transmitting end, a neighbor segment identifier is defined based on an improved SRv6 protocol, a bit path coding mechanism is constructed, a bitmap is obtained after coding, a neighbor forwarding table is constructed, and a data packet is sent according to the neighbor forwarding table; the intermediate node is a receiving end, a neighbor forwarding table of the intermediate node is constructed, a data packet is received, a bit sequence analysis method is executed to decode and update a bitmap in a neighbor segment identifier, the bitmap is compared with the neighbor forwarding table, and a forwarding interface and a forwarding data packet are obtained. The total length of the neighbor segment identifier is 128 bits, and the neighbor segment identifier structurally comprises an LOC field, an FUNCT field and an ARGS field; the LOC field occupies 64 bits and comprises a 4-bit CI (Consumption Identifier) and a 60-bit bitmap. According to the method, the segmented routing lightweight of satellite communication can be realized, the computing power consumption is reduced, the overhead is reduced, and the bandwidth utilization rate of inter-satellite links is improved.

The present application relates to big data processing and edge computing technical field, specifically to information big data management system based on edge computing, including mutation detection module, skip list management module and decision execution module, the mutation detection module carries out "noise-silence" dual-state detection to big data stream in edge node, only intercepts mutation micro-slice at state conversion and calculates 128 bit SimHash mutation fingerprint; the skip list management module weaves the "mutation fingerprint-physical block" bidirectional skip list with reversible fuse mark on local PCM, realizes the index of mutation fingerprint to physical block address; the decision execution module takes the skip list root handle as the entrance, drives the "write once" type edge inference machine to generate the immutable decision frame, writes back the data source terminal through the low delay channel and updates the fuse state, so as to complete the closed loop processing of cold mutation data.

The invention discloses an AES-GCM authentication encryption method and device with low resource consumption. The method comprises the following steps: firstly, acquiring input data, a symmetric key, an initial vector, to-be-processed data and additional authentication data; a key stream used for encryption is generated through a first processing process, the first processing process comprises the steps of executing AES encryption operation, and the AES encryption operation is completed through multi-cycle iteration with the bit width lower than 128 bits; under the condition that the to-be-processed data is the first plaintext, performing XOR operation on the first plaintext and the key stream to generate a first ciphertext; the authentication tag is generated through a second processing procedure, the second processing procedure comprises executing GHASH calculation, Galois field multiplication contained in the GHASH calculation is completed through multi-cycle iteration with the bit width lower than 128 bits, and the execution time sequence of the first processing procedure and the execution time sequence of the second processing procedure are scheduled to be at least partially overlapped. And the efficient AES-GCM authentication encryption processing is realized.

Processor (310) comprising: a decoding unit (314) for decoding a data element comparison instruction (312), wherein the data element comparison instruction (312) specifies a first packed source data operand (322) containing at least sixteen 8-bit data elements, a second packed source data operand (324) containing at least sixteen 8-bit data elements, and a mask register (332), wherein the sixteen 8-bit data elements contained in the first packed source data operand (322) and the sixteen 8-bit data elements contained in the second packed source data operand (324) each occupy 128 bits, wherein the sixteen 8-bit data elements contained in the first packed source data operand (322) specify the sixteen 8-bit data elements correspond to those contained in the second packed source data operand (324);and an execution unit (318) coupled to the decoding unit (314), wherein the execution unit (318), in response to the data element comparison instruction (312), performs a data element comparison operation for each of the sixteen 8-bit data elements in the first packed source data operand (322) with all of the sixteen 8-bit data elements in the second packed source data operand (324) and stores a result mask operand (328, 330) in the mask register (332), wherein the result mask operand (328, 330) contains a different mask bit with a value of 1 for each of the sixteen 8-bit data elements in the first packed source data operand (322) when an operation of the data element comparison operation determines that the data element in the first packed source data operand (322) matches any of the sixteen 8-bit data elements in the second packed source data operand (324), and otherwise returns a value of 0.;

This application provides a method, apparatus, device, and medium for dynamically adjustable block cipher algorithm structures, relating to the field of information security. The method includes: inputting a master key, master control parameters, and plaintext to be encrypted; iteratively executing 32 rounds of encryption operations using the master key and master control parameters on the plaintext until 128 bits of ciphertext are obtained. This application achieves dynamic adjustability of the cryptographic algorithm structure by adding parameter control, allowing for the generation of round functions with different structures through parameter adjustment, while simultaneously ensuring the algorithm's resistance to differential attacks. This enriches the diversity of block cipher algorithm structures and improves the algorithm's security.