A clock synchronization method and terminal

A clock synchronization and end-to-end technology, applied in the field of communication, can solve the problems of large data overhead and low communication efficiency, and achieve the effect of realizing clock synchronization and improving communication efficiency.

Active Publication Date: 2019-02-26
SICHUAN JIUZHOU ELECTRIC GROUP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The embodiment of the present invention provides a clock synchronization method and a terminal device, which are used to solve the technical problem that the clock synchronization method in the prior art has a large data overhead, which leads to low communication efficiency

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  • A clock synchronization method and terminal
  • A clock synchronization method and terminal
  • A clock synchronization method and terminal

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Embodiment Construction

[0031] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0032] The clock synchronization method in the embodiment of the present invention can be applied to the first terminal, wherein both the first terminal and the subsequent second terminal can belong to the SC-FDE system, and the SC-FDE system is a single-carrier system. There is an inherent peak to average power ratio (Peak to Average Power R...

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Abstract

The invention provides a clock synchronization method and a terminal machine. The clock synchronization method comprises the following steps: receiving a first transmission frame sent by a second terminal machine connected with a first terminal machine, wherein the first transmission frame includes a pilot sequence and user data, and at least part of data of the pilot sequence can be used as a cyclic prefix in the first transmission frame to eliminate the multi-path interference to the transmission channel between the first terminal machine and the second terminal machine; acquiring time error information based on the first transmission frame, wherein the time error information is used to indicate the phase difference between a first clock signal generated when the second terminal machine sends the first transmission frame and a second clock signal generated when the first terminal machine receives the first transmission frame; determining a first sampling point for sampling the user data in the first transmission frame and a second sampling point for sampling the pilot sequence in the first transmission frame based on the time error information; and carrying out clock synchronization between the first terminal machine and the second terminal machine based on the first sampling point and the second sampling point.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to a clock synchronization method and a terminal. Background technique [0002] Communication technology has made great progress in recent decades, especially since the 1990s, and has had a profound impact on people's daily life and the development of the national economy. When the future communication technology is developing towards high-speed bandwidth, many broadband digital transmission technologies have received extensive attention, such as Orthogonal Frequency Division Multiplexing (Orthogonal Frequency Division Multiplexing, OFDM), Frequency Domain Equalization Single Carrier (Single Carrier With Frequency Domain Equalization, SC-FDE), etc. [0003] At present, the clock synchronization of the SC-FDE system usually adopts a data-assisted clock synchronization method, that is, the sending end sends a known fixed sequence before sending the data frame, and the receiving...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/06H04L5/00
CPCH04J3/0638H04L5/0048
Inventor 何奎龙彭青建蒲祥东
Owner SICHUAN JIUZHOU ELECTRIC GROUP
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