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Forming interconnect features with reduced sidewall tapering

A technology of dielectric layer and hard mask layer, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as reducing density

Inactive Publication Date: 2017-08-18
GLOBALFOUNDRIES INC +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This sidewall taper requires increased spacing between adjacent vias to provide sufficient electrical separation, reducing the density

Method used

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  • Forming interconnect features with reduced sidewall tapering
  • Forming interconnect features with reduced sidewall tapering
  • Forming interconnect features with reduced sidewall tapering

Examples

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Embodiment Construction

[0011] Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It should be understood that with the development of any such practical implementation, a number of implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. One. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but nonetheless, the present invention will be helpful to the routine work of those of ordinary skill in the art.

[0012] The subject matter will now be described with reference to the accompanying drawings. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as not to obscure the present disclosure with de...

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Abstract

The invention relates to forming interconnect features with reduced sidewall tapering. A method includes forming a stack of materials including a first dielectric layer having a conductive feature positioned therein, and a second dielectric layer positioned above the first dielectric layer. An etch mask including a plurality of spaced apart mask elements is formed above the second dielectric layer. The mask elements define at least a first via opening exposing the second dielectric layer. A patterning layer is formed above the etch mask. A second via opening is formed in the patterning layer to expose the first via opening in the etch mask. The second dielectric layer is etched through the second via opening to define a third via opening in the second dielectric layer exposing the conductive feature. The patterning layer and the etch mask are removed. A conductive via contacting the conductive feature is formed in the third via opening.

Description

technical field [0001] The subject matter of the present invention relates generally to the fabrication of semiconductor devices, and more particularly to forming interconnect features, such as vias or lines, with reduced sidewall taper. Background technique [0002] The minimum feature size of modern integrated circuits (such as the channel length of field effect transistors) has reached the deep sub-micron range, thereby steadily increasing in speed and / or power consumption and / or circuit function performance of these circuits. The size of the individual circuit components is significantly reduced, thereby increasing the switching speed of, for example, transistor components, and also the floor space available for the individual circuit components to be electrically connected to interconnect lines. Therefore, the size of these interconnect lines and the space between the metal lines must be reduced to compensate for the reduced amount of available area and the increased n...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768
CPCH01L21/76877H01L21/76808H01L21/76897H01L21/76811H01L21/76816H01L21/0337H01L21/31144
Inventor F·W·莫恩特S·西迪基D·M·特里克特B·C·佩埃萨拉
Owner GLOBALFOUNDRIES INC