Multiplying device, data processing method, chip and electronic equipment

A multiplier and data technology, applied in the computer field, can solve the problem of high complexity of multiplication operations, and achieve the effect of reducing complexity

Pending Publication Date: 2019-10-22
SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the traditional technology, the number of non-zero bit values ​​in the code is large, and the number of correspondi

Method used

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  • Multiplying device, data processing method, chip and electronic equipment
  • Multiplying device, data processing method, chip and electronic equipment
  • Multiplying device, data processing method, chip and electronic equipment

Examples

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Embodiment Construction

[0069] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

[0070] The multiplier provided by this application can be applied to AI chips, field programmable gate array FPGA (Field-Programmable Gate Array, FPGA) chips, or other hardware circuit devices for multiplication processing. The specific structural diagram is as follows figure 1 and 2 shown.

[0071] Such as figure 1 as shown, figure 1 A structure diagram of a multiplier provided for an embodiment. Such as figure 1 As shown, the multiplier includes: a modified regular signed number encoding circuit 11 and a modified compression circuit 12; the output end of the modifie...

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Abstract

The invention provides a multiplier, a data processing method, a chip and electronic equipment. The multiplier comprises a multiplier unit; judgment circuit, a data expansion circuit, a regular sign number encoding circuit and a compression circuit. The output end of the judgment circuit is connected with the input end of the data expansion circuit. The output end of the judgment circuit is connected with the first input end of the regular signed number encoding circuit. The output end of the data expansion circuit is connected with the second input end of the regular symbolic number encodingcircuit. The output end of the regular signed number encoding circuit is connected with the input end of the compression circuit. The multiplier can carry out regular signed number encoding on received data through the regular signed number encoding circuit. The number of obtained effective partial products is small. Therefore, the complexity of multiplication operation achieved by the multiplieris reduced.

Description

technical field [0001] The present application relates to the field of computer technology, in particular to a multiplier, a data processing method, a chip and electronic equipment. Background technique [0002] With the continuous development of digital electronic technology, the rapid development of various artificial intelligence (AI) chips has higher and higher requirements for high-performance digital multipliers. The neural network algorithm is one of the algorithms widely used in smart chips, and the multiplication operation through the multiplier is a common operation in the neural network algorithm. [0003] At present, the multiplier uses every three-digit value in the multiplier as a code, and obtains partial products according to the multiplicand, and uses Wallace tree to compress all partial products to obtain the result of multiplication. However, in the conventional technology, the number of non-zero bit values ​​in the code is large, and the number of corres...

Claims

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Application Information

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IPC IPC(8): G06F7/53G06F7/533G06F7/48G06N3/063
CPCG06F7/5318G06F7/5332G06F7/4824G06N3/063
Inventor 不公告发明人
Owner SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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