Design method for optimizing fishbone type clock tree metal wiring

Abstract

The invention discloses a design method for optimizing fishbone type clock tree metal wiring. The method comprises the following steps of: 1) before logic units in a chip are placed, dividing an integral module into squares with the side length of 30 microns, and specifying the placing density of the logic units in each square so that the logic units are uniformly distributed; 2) taking out the vertical coordinates of the adjacent fishbone branches, calculating the distance between the adjacent fishbone branches, recording the distance as a, and creating a transverse routing blockage at the central point of each adjacent branch; 3) taking the fishbone tree trunk as a starting point, taking a as an interval, and respectively creating longitudinal routing blockages leftwards and rightwards;and 4) capturing the line name of the fishbone type clock tree connected with the load of the fishbone type clock tree, preferentially performing metal routing on the connecting lines, deleting metalrouting blockages after routing is completed, and then performing global wiring. The method saves interconnection line resources, optimizes the clock structure and improves the clock quality.

Description

technical field [0001] The invention designs a design method for optimizing metal wiring of a fishbone clock tree. Background technique [0002] Due to the complexity of the clock structure, when the tool automatically grows the clock tree, in order to balance the clock tree so that the clock signal starts from the same clock source and has the same delay to the clock end of each register, a buffer is usually added to the shorter path. At the same time, the short path is detoured far away, so that the clock delays of the short path and the longer path are balanced to be consistent. With the advancement of technology and the continuous shrinking of feature size, the interconnection delay has become the main delay unit on the timing path. Therefore, this way of winding the far metal line and inserting the buffer of the balance unit virtually increases the winding distance, making the clock signal The propagation delay is greatly increased, resulting in increased power consump...

AI Technical Summary

Problems solved by technology

This is contrary to the original intention of the design, and will cause the main load to be too large, resulting in a large clock conversion time delay, thereby affecting the clock quality, so it is necessary to avoid the situation that the load and the main body have metal connections

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