FPGA one-dimensional signal identification neural network acceleration method based on OpenCL

A neural network and signal recognition technology, applied in the field of convolutional neural network acceleration, can solve problems such as system performance degradation

Active Publication Date: 2021-05-18
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Problems solved by technology

However, due to the Power-Law characteristics of graphs, communication between graph nodes, random access memory and other issues that are common in graph computing, system performance will decline.

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  • FPGA one-dimensional signal identification neural network acceleration method based on OpenCL
  • FPGA one-dimensional signal identification neural network acceleration method based on OpenCL
  • FPGA one-dimensional signal identification neural network acceleration method based on OpenCL

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Embodiment Construction

[0020] The specific implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific examples.

[0021] Such as Figure 1~2 As shown, the OpenCL-based FPGA one-dimensional signal recognition neural network acceleration method specifically includes the following steps:

[0022] 1) Construct a one-dimensional convolutional neural network on the CPU host side;

[0023] 2) read the one-dimensional signal data with a size of 8192*1 and the weight and bias data used for signal data convolution obtained from training into the host memory from the text file;

[0024] 3) Calculate the first convolutional layer of the convolutional neural network:

[0025] 3a) read the signal data obtained after the signal data in step 2) through edge extension processing, and the weight and bias data used by the convolution layer into the FPGA global memory;

[0026] 3b) Call the convolution kernel function to let the...

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Abstract

The invention discloses a method for accelerating a signal identification convolutional neural network on an FPGA (Field Programmable Gate Array) based on an OpenCL standard. The method comprises the following steps: constructing a one-dimensional convolutional neural network at a CPU (Central Processing Unit) host end; obtaining and reading one-dimensional signal data and weight and bias data used for signal data convolution through training into an FPGA global memory; when entering one layer of the convolutional neural network, reading data required by calculation into an FPGA global memory, calling a corresponding kernel function to perform operation on the FGPA, and returning a result to a CPU host end after the operation is finished; and returning an operation result of the whole convolutional neural network to the CPU, and recording operation time consumption. The CPU + FPGA heterogeneous architecture can better achieve high-performance parallel computing, meanwhile, the FPGA has the large data throughput, the floating point computing capacity is higher than that of a CPU, the FPGA is more suitable for data intensive computing tasks, and the speed of the convolutional neural network algorithm is greatly increased under the condition that the accuracy of the neural network algorithm is kept.

Description

technical field [0001] The invention belongs to the technical field of wireless communication, and in particular relates to an acceleration method of a convolutional neural network based on an OpenCL-based FPGA heterogeneous platform for one-dimensional signal recognition. Background technique [0002] In recent years, communication technology has developed rapidly. In order to meet the different needs of users, make full use of communication resources, and improve spectrum utilization, the system and modulation methods of communication signals have become diversified and complicated, and signals in the same space have become more and more complex. dense. In the design of the electronic warfare communication intelligence interception receiver, the modulation method of the received communication signal is obtained, which provides a reference basis for the demodulator to select the demodulation algorithm, which is helpful for the selection of the best interference pattern or i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/04G06N3/08G06K9/00G06F15/78
CPCG06N3/08G06F15/7807G06V10/95G06N3/048
Inventor 李建清谢安东王宏
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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