FPGA one-dimensional signal recognition neural network acceleration method based on opencl

A neural network and signal recognition technology, applied in the field of acceleration of convolutional neural networks, can solve problems such as system performance degradation, achieve large data throughput, increase computing speed, and achieve the effect of high-performance parallel computing

Active Publication Date: 2022-06-24
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Problems solved by technology

However, due to the Power-Law characteristics of graphs, communication between graph nodes, random access memory and other issues that are common in graph computing, system performance will decline.

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  • FPGA one-dimensional signal recognition neural network acceleration method based on opencl
  • FPGA one-dimensional signal recognition neural network acceleration method based on opencl
  • FPGA one-dimensional signal recognition neural network acceleration method based on opencl

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Embodiment Construction

[0020] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0021] like Figures 1 to 2 As shown, the FPGA one-dimensional signal recognition neural network acceleration method based on OpenCL specifically includes the following steps:

[0022] 1) Build a one-dimensional convolutional neural network on the CPU host side;

[0023] 2) Read the one-dimensional signal data with a size of 8192*1 and the weight and bias data for convolution of the signal data obtained by training into the host memory from the text file;

[0024] 3) Calculate the first convolutional layer of the convolutional neural network:

[0025] 3a) the signal data obtained after the edge expansion processing of the signal data in step 2), and the weight and bias data used by the convolution layer are read into the FPGA global memory;

[0026] 3b) Call the convolution kernel function to operate the d...

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Abstract

An acceleration method for signal recognition convolutional neural network on FPGA based on OpenCL standard, constructing a one-dimensional convolutional neural network on the CPU host side; one-dimensional signal data and training to obtain weight and bias data for signal data convolution , read into the FPGA global memory; each time it enters a layer of the convolutional neural network, read the data required for calculation into the FPGA global memory, and call the corresponding kernel function to perform calculations on the FPGA, and return the results to the CPU host after the calculation is completed; The result of the entire convolutional neural network operation is returned to the CPU, and the time-consuming operation is recorded. The CPU+FPGA heterogeneous architecture of the present invention can better realize high-performance parallel computing. At the same time, FPGA has a large data throughput, and its computing power for floating points is higher than that of CPU, which is more suitable for data-intensive computing tasks. While maintaining the accuracy of the neural network algorithm, the speed of the convolutional neural network algorithm is greatly improved.

Description

technical field [0001] The invention belongs to the technical field of wireless communication, and in particular relates to an acceleration method of a convolutional neural network for one-dimensional signal recognition by an OpenCL-based FPGA heterogeneous platform. Background technique [0002] In recent years, with the rapid development of communication technology, in order to meet the different needs of users, make full use of communication resources, and improve spectrum utilization, the systems and modulation methods of communication signals have become diversified and complicated, and the signals in the same space have become more and more dense. In the design of the electronic warfare communication intelligence interception receiver, the modulation mode of the received communication signal is obtained, which provides a reference for the demodulator to select the demodulation algorithm, which is helpful for the selection of the best interference pattern or interferenc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06N3/04G06N3/08G06K9/00G06F15/78
CPCG06N3/08G06F15/7807G06V10/95G06N3/048
Inventor 李建清谢安东王宏
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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