Matching and harmonic suppression system and method based on navigation receiver clock link
A navigation receiver and harmonic suppression technology, which is applied to radio wave measurement systems, satellite radio beacon positioning systems, instruments, etc., can solve the problems of affecting positioning accuracy, increasing harmonic components, and lack of effective processing, so as to achieve convenient implementation , the effect of simple structure
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Embodiment 1
[0051] A matching and harmonic suppression system based on the clock link of the navigation receiver, which realizes the optimization of the clock and improves the capture effect of the receiver, such as figure 1 As shown, including TCXO, level conversion circuit, combined filter circuit, clockbuffer clock drive circuit, radio frequency, ADC, signal processing end;
[0052] The peak-clipping sine wave is output through the TCXO, and the peak-clipping sine wave is level-shifted by the level conversion circuit, filtered by the combined filter circuit, and then adjusted to the LVCMOS level by the voltage regulation circuit and output to the clockbuffer clock drive circuit. 10 clock signals, 10 clock signals are filtered and attenuated through the combined filter circuit, 8 of the output clock signals are output to the radio frequency, and 1 clock signal is output to the signal processing terminal, and the frequency multiplication output from the signal processing terminal is combi...
Embodiment 2
[0054] A matching and harmonic suppression system based on the clock link of a navigation receiver according to Embodiment 1.
[0055] The model of the TCXO is RPT5032A, its phase noise is less than -160dBc / Hz, the phase jitter is less than 0.13ps, and the frequency stability can reach as low as 0.05ppm; the model of the radio frequency is MAX2771, the model of the signal processing end is ZYNQ XC7Z035, and the model of the ADC is AD9628.
[0056] The level conversion circuit includes a power supply 3V3_CB, a resistor R4, and a resistor R5;
[0057] One end of the resistor R4 (1kΩ) is connected to the power supply 3V3_CB (3.3V), the other end is connected to one end of the resistor R5 (1kΩ), the other end of the resistor R5 is connected to the ground network GND_CB, and the connected end of the resistor R4 and the resistor R5 is coupled with a DC signal (1.65DC).
[0058] The combined filter circuit includes a T-type filter circuit and a π-type circuit; the T-type filter circu...
Embodiment 3
[0088] Embodiment 1 or 2 is based on the working method of the matching of the navigation receiver clock link and the harmonic suppression system, such as Figure 5 shown, including the following steps:
[0089] (1) Output peak clipping sine wave through low phase noise TCXO;
[0090] (2) The peak-cut sine wave is level-converted by a level conversion circuit, and filtered by a combined filter circuit to generate a clock signal;
[0091] (3) Adjust the clock signal generated in step (2) to the LVCMOS level and output it to the clockbuffer clock drive circuit through the voltage regulating circuit, and output 10 clock signals;
[0092] (4) The 10 clock signals output by step (3) are filtered and attenuated by the combined filter circuit;
[0093] (5) After filtering and attenuating 10 clock signals, 8 clock signals are sent to the radio frequency, and 1 clock signal is sent to the signal processing end;
[0094] (6) The synchronous clock signal is output to the sampling ADC ...
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