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Matching and harmonic suppression system and method based on navigation receiver clock link

A navigation receiver and harmonic suppression technology, which is applied to radio wave measurement systems, satellite radio beacon positioning systems, instruments, etc., can solve the problems of affecting positioning accuracy, increasing harmonic components, and lack of effective processing, so as to achieve convenient implementation , the effect of simple structure

Active Publication Date: 2021-10-26
SHANDONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, the positioning accuracy of high-precision satellite receiver boards is closely related to the quality of their clock signals. On-board high-precision clocks mainly include TCXO (temperature-compensated crystal oscillator) and OCXO (constant temperature crystal oscillator). Although OCXO has higher precision, it is smaller in size. Large, it is difficult to integrate on the baseband board, so the TCXO crystal oscillator is commonly used at present
[0003] At present, the clock input requirements of RF and baseband chips are basically greater than 0.8Vpp, so in order to improve accuracy and reduce power consumption, the current TCXO output is mostly clipped sine wave (Clippedsin), and the output of peak clipped sine wave will increase the output harmonic At the same time, the duty cycle of the TCXO output is difficult to reach a perfect 50% due to the interference of the crystal oscillator manufacturer's production process and PCB design, so even harmonics will be generated. Combined with the above reasons, the 5th harmonic of the TCXO output The increase of energy in the wave will interfere with the baseband capture effect and ultimately affect the positioning accuracy. However, the clock source of the current high-precision positioning receiver lacks effective processing. Most of the clock links are connected to the clock receiving end through 10nF capacitors.

Method used

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  • Matching and harmonic suppression system and method based on navigation receiver clock link
  • Matching and harmonic suppression system and method based on navigation receiver clock link
  • Matching and harmonic suppression system and method based on navigation receiver clock link

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0051] A matching and harmonic suppression system based on the clock link of the navigation receiver, which realizes the optimization of the clock and improves the capture effect of the receiver, such as figure 1 As shown, including TCXO, level conversion circuit, combined filter circuit, clockbuffer clock drive circuit, radio frequency, ADC, signal processing end;

[0052] The peak-clipping sine wave is output through the TCXO, and the peak-clipping sine wave is level-shifted by the level conversion circuit, filtered by the combined filter circuit, and then adjusted to the LVCMOS level by the voltage regulation circuit and output to the clockbuffer clock drive circuit. 10 clock signals, 10 clock signals are filtered and attenuated through the combined filter circuit, 8 of the output clock signals are output to the radio frequency, and 1 clock signal is output to the signal processing terminal, and the frequency multiplication output from the signal processing terminal is combi...

Embodiment 2

[0054] A matching and harmonic suppression system based on the clock link of a navigation receiver according to Embodiment 1.

[0055] The model of the TCXO is RPT5032A, its phase noise is less than -160dBc / Hz, the phase jitter is less than 0.13ps, and the frequency stability can reach as low as 0.05ppm; the model of the radio frequency is MAX2771, the model of the signal processing end is ZYNQ XC7Z035, and the model of the ADC is AD9628.

[0056] The level conversion circuit includes a power supply 3V3_CB, a resistor R4, and a resistor R5;

[0057] One end of the resistor R4 (1kΩ) is connected to the power supply 3V3_CB (3.3V), the other end is connected to one end of the resistor R5 (1kΩ), the other end of the resistor R5 is connected to the ground network GND_CB, and the connected end of the resistor R4 and the resistor R5 is coupled with a DC signal (1.65DC).

[0058] The combined filter circuit includes a T-type filter circuit and a π-type circuit; the T-type filter circu...

Embodiment 3

[0088] Embodiment 1 or 2 is based on the working method of the matching of the navigation receiver clock link and the harmonic suppression system, such as Figure 5 shown, including the following steps:

[0089] (1) Output peak clipping sine wave through low phase noise TCXO;

[0090] (2) The peak-cut sine wave is level-converted by a level conversion circuit, and filtered by a combined filter circuit to generate a clock signal;

[0091] (3) Adjust the clock signal generated in step (2) to the LVCMOS level and output it to the clockbuffer clock drive circuit through the voltage regulating circuit, and output 10 clock signals;

[0092] (4) The 10 clock signals output by step (3) are filtered and attenuated by the combined filter circuit;

[0093] (5) After filtering and attenuating 10 clock signals, 8 clock signals are sent to the radio frequency, and 1 clock signal is sent to the signal processing end;

[0094] (6) The synchronous clock signal is output to the sampling ADC ...

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Abstract

The invention relates to a matching and harmonic suppression system and method based on a navigation receiver clock link. The matching and harmonic suppression system comprises a TCXO, a level conversion circuit, a combined filter circuit, a clock buffer clock driving circuit, a radio frequency unit, an ADC and a signal processing end. A peak clipping sine wave is output through a TCXO, level conversion is carried out through a level conversion circuit, filtering is carried out through a combined filter circuit, a signal is adjusted to an LVCMOS level through a voltage regulation circuit, the signal is output to a clock buffer clock driving circuit, 10 paths of clock signals are output, the 10 paths of clock signals are respectively filtered and attenuated through the combined filter circuit, and 8 paths of clock signals are output to a radio frequency. One path of clock signal is output to a signal processing end, and a synchronous clock signal is output to a sampling ADC through a combined filter circuit so as to complete the processing of a clock link. According to the invention, the quality of the TCXO clock output signal is improved, and the harmonic wave of the local oscillator signal is reduced.

Description

technical field [0001] The invention relates to an impedance matching and harmonic suppression system and method of a clock signal in a transmission link of a clock source in a global satellite navigation system receiver, so as to improve the capture effect of the receiver. Background technique [0002] The current global satellite navigation system is developing rapidly, and Beidou-3 has successfully established a comprehensive network to help the development of global navigation and positioning systems. At present, the global satellite navigation system is mainly divided into four major satellites including Beidou (BDS), GPS, Galileo, and GLONASS Navigation System. At present, the positioning accuracy of high-precision satellite receiver boards is closely related to the quality of their clock signals. The on-board high-precision clocks mainly include TCXO (temperature-compensated crystal oscillator) and OCXO (constant temperature crystal oscillator). Although OCXO has high...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01S19/37
CPCG01S19/37
Inventor 邢建平董彦辰刘世杰韩帅代培培孟志扬
Owner SHANDONG UNIV