Binary decision diagram construction method, equivalence verification method and storage medium

Abstract

The invention discloses a binary decision diagram construction method, an equivalence verification method and a storage medium. The binary decision diagram construction method comprises the following steps: an iteration process of determining a cone top and a cone bottom of a circuit, and generating a binary decision diagram from an input port of the cone top; when the iteration process is carried out to the connection network part, if the current connection network is not in a multi-drive mode and the number of the ports connected with the connection network is larger than or equal to 3, searching the hash table; if the local binary decision diagram is not found, continuing an iteration process capable of generating the binary decision diagram to generate a local binary decision diagram corresponding to the connection network, and storing the local binary decision diagram into a hash table; and traversing to the connection network in an iteration process, and directly taking out the connection network from the hash table. In the process of generating the BDD, the time and memory consumed for processing the BDD graph are reduced, so that the verification time of the circuit is greatly shortened.

Description

technical field [0001] The invention relates to the technical field of equivalence verification of digital circuits, in particular to a method for constructing a binary decision graph. Background technique [0002] One of the most extensive verification methods in the current logic verification technology of combinational circuits is based on the BDD (BinaryDecision Diagram, binary decision diagram) method. Its principle is to prove that the ROBDD (Reduced Ordered Binary Decision Diagram, statute Ordered binary decision diagram) is isomorphic, if isomorphic, it means that the two design circuits are equivalent. [0003] BDD itself is also a data structure that can be used to describe large Boolean functions, and can also describe all options at the same time, but due to the unpredictable memory requirements, it is difficult to process special circuits (such as multiplication circuits) and large-scale integration. Circuits will encounter insurmountable difficulties. [0004...

Images