Simulation circuit reliability simulation method based on dynamic step length
An analog circuit and dynamic step size technology, applied in the field of computer simulation, can solve the problems of long simulation time, circuit performance degradation, simulation error, etc. Effect
Pending Publication Date: 2022-07-01
XIDIAN UNIV
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Problems solved by technology
[0006] First, the current degradation model theory proves that the degradation amount of device parameters in the degradation circuit will gradually tend to be saturated as the degradation time becomes longer, so if the set step size is too small, it will lead to more accurate degradation in the early stage. As a result, but the degradation gradually tends to be saturated in the later stage, which will bring meaningless simulation, resulting in too long simulation time
[0007] Second, if the set step size is too large, the simulation error caused by the change of the bias condition caused by the degradation will still be caused when the degradation speed is fast in the early stage, resulting in insufficient reliability simulation accuracy
[0008] In response to the above problems, some scholars have also proposed the method of adaptive step size, that is, according to the amount of circuit performance degradation, the step size is set to an adaptive step size that changes continuously with the change of circuit performance through some calculations, but there are still some problems in these methods. Problem: First of all, the change in circuit performance may not be directly related to the degradation of the devices in the circuit. Some devices have little degradation, but they will degrade the circuit performance a lot, so even if the step size is reduced, it will not make the circuit simulation more accurate. Accurate; secondly, the number of steps of the above adaptive step size method is uncertain, it may be dozens of steps, or it may be hundreds of steps, which will cause the calculation time of circuit simulation to become unbearable
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[0035] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.
[0036] refer to image 3 , the specific implementation steps of this example are as follows:
[0037] Step 1, read the circuit netlist and calculate the initial step size.
[0038] 1.1) Set the circuit structure, model library file, simulation conditions and reliability simulation parameters of the inverter to form an inverter circuit netlist file as the input file required for the subsequent inverter reliability simulation;
[0039] 1.2) Read the parameters required for reliability simulation from the inverter circuit netlist, the degradation time T age = 2...
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The invention discloses an analog circuit reliability simulation method based on dynamic step length, and mainly solves the problems that the prior art cannot fit the actual degradation condition of a device, and the simulation precision and speed cannot be considered at the same time. According to the implementation scheme, the method comprises the following steps: reading set degradation time T and s step lengths from a circuit simulation input file; calculating initial step length time t0 = T / s, and assigning the initial step length time t0 to each step length; inputting a device degradation model function, and calculating a degradation rate function f (t) along with time; performing scaling calculation on s step lengths with values of t0 through degradation rates f (t) of a device degradation function at different moments to obtain a group of dynamic step lengths; and performing circuit reliability simulation by using the dynamic step length to obtain a degradation result of the circuit characteristic index. According to the method, the reliability simulation precision is improved, the reliability simulation time is budgeted to be controllable by setting the step length number of simulation, and the method can be used for predicting the degeneration relation of circuit performance along with time and the service life of the circuit.
Description
technical field [0001] The invention belongs to the technical field of computer simulation, and in particular relates to a circuit reliability simulation method, which can be used to predict the degradation relationship of circuit performance over time and the life of the circuit. Background technique [0002] With the continuous development of Moore's Law, the current device size is getting smaller and smaller, and the circuit scale is getting larger and larger, which will bring more serious non-ideal effects, such as hot carrier injection effect HCI, bias temperature instability BTI etc., these non-ideal effects will make some important parameters of the device such as threshold voltage continue to degrade over time, resulting in reduced circuit life. At present, in order to consider the life of the circuit, major EDA manufacturers and some colleges and universities have begun to pay attention to the reliability simulation of the circuit. Through the circuit reliability si...
Claims
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IPC IPC(8): G06F30/367G06F17/10G06F119/02G06F119/12
CPCG06F30/367G06F17/10G06F2119/02G06F2119/12
Inventor李聪董啸宇吕松松成善霖游海龙
OwnerXIDIAN UNIV