Method for manufacturing semiconductor device

a manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, electrical appliances, transistors, etc., can solve the problems of increasing production costs, reducing yield, and difficulty in achieving high wiring density

Inactive Publication Date: 2005-08-25
ELPIDA MEMORY INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The present invention provides a method of manufacturing a semiconductor that prevents resist residue on a gate opening portion when forming a gate opening portion finely for injecting an impurity to form an asymmetric transistor during a process of patterning a gate electrode. The method includes a process of forming a first semiconductor region and a second semiconductor region at a period of time during the gate electrode patterning process. The method also includes steps of forming a trench in the semiconductor layer and then forming the first and second semiconductor regions. The first and second stages of the gate electrode patterning process can be followed in either order. The method can also include making the first semiconductor region deeper or having higher impurity concentration than the second semiconductor region. Overall, this method prevents resist residue and improves the manufacturing process of semiconductors."

Problems solved by technology

Regarding wirings for connecting between a CPU (Central Processing Unit) and semiconductor regions each making up the memory cell, it is difficult to achieve a high wiring density matched to a high integration by the wirings formed in only a planar direction on a semiconductor substrate.
This causes a decrease in the yield, and as a result increases production costs.

Method used

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  • Method for manufacturing semiconductor device
  • Method for manufacturing semiconductor device
  • Method for manufacturing semiconductor device

Examples

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first embodiment

[0061] FIGS. 1 to 8 are process diagrams for showing a method or manufacturing a semiconductor device in order or processes according to a first embodiment of the present invention. The method of manufacturing the semiconductor device in order of processes will be described referring to FIGS. 1 to 8 as follows. Furthermore in FIGS. 2A to 6A, FIG. A is a cross-sectional view of FIGS. 2B to 6B, respectively taken along a line A-A.

[0062] At first, as shown in FIG. 1, a device isolation insulating layer 2, which is made up of a silicon dioxide (SiO2), for example, and insulates between devices, is selectively buried and formed in, for example, a P (positive)-type silicon semiconductor substrate 1, by using a well-known STI (Shallow Trench Isolation) method. Next, after forming a gate insulating film 3 made of a silicon dioxide with a thickness of 2˜10 nm by a thermal oxidation method, a gate conductive film 4A made of a poly-silicon with a thickness of 0.2˜1.0 μm and a first interlayer...

second embodiment

[0073] FIGS. 9 to 12 are process diagrams for showing a main process of a method of manufacturing a semiconductor device according to a second embodiment of the present invention. A significant difference between configuration of the method of manufacturing a semiconductor of the first embodiment and the configuration of the method of manufacturing a semiconductor of the second embodiment is that one process of a gate electrode patterning to form a semiconductor region to be connected to a capacitive element via a capacitive contact is carried out in advance of another process of the gate electrode patterning to form a semiconductor region to be connected to a bit line via a bit contact. Hereinafter, the method of manufacturing the semiconductor device according to the second embodiment will be described in order of processes referring to FIGS. 9 to 12.

[0074] First, as shown in FIG. 9, a device isolation insulating layer 2, which is made up of a silicon dioxide (SiO2), for example,...

third embodiment

[0080] FIGS. 13 to 18 are process diagrams for showing a main process of a method of manufacturing a semiconductor device according to a third embodiment of the present invention. A significant difference of configurations of the method of processing the semiconductor device in the embodiment compared with configurations of the method of processing the semiconductor device described in first and second embodiments is that a memory cell is made up of an asymmetric transistor. Hereafter, the method of manufacturing the semiconductor device according to the third embodiment will be described in order of processes referring to FIGS. 13 to 18.

[0081] At first, as shown in FIG. 13, a device isolation insulating layer 2, which is made up of a Silicon dioxide (SiO2), for example, and insulates between devices, is selectively buried and formed in, for example, a P (positive)-type a semiconductor substrate 28, by using a well-known STX (Shallow Trench Isolation) method. And, a trench portion ...

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Abstract

Provided is a method of manufacturing a semiconductor device capable avoiding occurrence of resist residue on a gate opening portion when forming the gate opening portion finely for injecting an impurity to form an asymmetric transistor during patterning of a gate electrode. The method of manufacturing the semiconductor device, in a case of manufacturing a DRAM (Dynamic Random Access Memory) with a memory cell transistor made up of the asymmetric transistor, performs separately a first gate electrode patterning process for forming a high concentration N-type diffusion region to be electrically connected to a capacitive element via a capacitive contact connect, and a gate second electrode patterning process for forming a high concentration N-type diffusion region to be electrically connected to a bit line via a bit contact.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to the method for manufacturing the semiconductor device, such as a DRAM (Dynamic Random Access Memory) including a plurality of memory cells each made up of an asymmetrical transistor. [0003] The present application claims priority of Japanese Patent Application No. 2004-045120 filed on Feb. 20, 2004, which is hereby incorporated by reference. [0004] 2. Description of the Related Art [0005] An LSI (Large Scale Integrated Circuit), known as a typical semiconductor device, is broadly classified into two kinds of devices, a memory device and a logic device. In a recent semiconductor manufacturing technology, improvement of a memory device manufacturing technology is especially remarkable. This memory device is further classified into two kinds of memory devices, a volatile memory device and a nonvolatile memory de...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L21/336H01L21/8242H01L27/108
CPCH01L27/10811H01L27/10873H01L29/66621H01L29/66537H01L27/10876H10B12/312H10B12/05H10B12/053
InventorUTSUNOMIYA, HIROYUKI
OwnerELPIDA MEMORY INC