Method for manufacturing electronic circuits integrated on a semiconductor substrate
a technology of electronic circuits and semiconductors, applied in the manufacturing of semiconductor/solid-state devices, basic electric elements, electric devices, etc., can solve the problems of reducing the size of lithographed structures, not being able to reduce the distance between two or more structures, and worsening the final defect rate of circuit structures to be realized
Inactive Publication Date: 2006-04-06
STMICROELECTRONICS SRL
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Problems solved by technology
Although advantageous into many respects, this first solution only allows the size of a lithographed structure to be reduced, but it is not suitable to reduce the distance between two or more structures.
While being advantageous from various points of view, this method for manufacturing spacers narrowing a window previously defined by lithography, has some drawbacks because of the complex circuit architecture made of a succession of depositions and etchings (both isotropic and anisotropic).
In particular, the large number of depositions and etchings greatly worsen the final defect rate of the circuit structure to be realized.
In general, particle contaminations deteriorate and heavily worsen the electric characteristics of an integrated circuit.
In addition, the precision with which the width of the spacers can be controlled has strict limits.
Accordingly, the accuracy of dimensional control after opening the second window is likely to drop to unsatisfactory levels.
Furthermore, manufacturing costs grow in proportion to the number of operations involved.
Method used
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[0035] Embodiments of a method for manufacturing electronic circuits integrated on a semiconductor substrate are described herein. In the following description, numerous specific details are given to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
[0036] Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not ...
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A method for manufacturing semiconductor-integrated electronic circuits includes: depositing an auxiliary layer on a substrate; depositing a layer of screening material on the auxiliary layer; selectively removing the layer of screening material to provide a first opening in the layer of screening material and expose an area of the auxiliary layer; and removing this area of the auxiliary layer to form a second opening in the auxiliary layer, whose cross-section narrows toward the substrate to expose an area of the substrate being smaller than the area exposed by the first opening.
Description
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a continuation of U.S. patent application Ser. No. 10 / 428,338, filed May 1, 2003, currently pending, which application is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present disclosure relates to a method for manufacturing electronic circuits integrated on a semiconductor substrate. [0004] The disclosure further relates to a method for manufacturing semiconductor-integrated electronic circuits comprising: [0005] depositing an auxiliary layer on a substrate; [0006] depositing a layer of screening material on said auxiliary layer; [0007] selectively removing said layer of screening material to provide a first opening in said layer of screening material and expose an area of said auxiliary layer. [0008] In particular, though not limited to, the disclosure relates to a method for defining circuit structures of submicron size, wherein the distance...
Claims
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IPC IPC(8): H01L21/8238H01L21/302H01L21/027H01L21/033H01L21/308H01L21/311H01L21/3213H01L21/768H01L21/8234
CPCH01L21/0276H01L21/0332H01L21/0337H01L21/0338H01L21/3081H01L21/3086H01L21/3088H01L21/31138H01L21/31144H01L21/32139H01L21/76804H01L21/76816H01L21/823437
Inventor CIOVACCO, FRANCESCOALBA, SIMONECOLOMBO, ROBERTOSAVARDI, CHIARA
Owner STMICROELECTRONICS SRL