Method of producing semiconductor

a production method and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device testing/measurement, electrical equipment, etc., can solve the problems of considerable significant and difficulty in minimizing the fluctuation in transistor characteristics between wafers or production lots

Active Publication Date: 2010-08-05
UNISANTIS ELECTRONICS SINGAPORE PTE LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Firstly, in the above process flow, dry etching for the pillar-shaped silicon layer has to be performed under etching conditions including a designated etching time, because it is unable to employ an end-point detection process based on monitoring of a change in plasma emission intensity. In this case, a height dimension of the pillar-shaped silicon layer is directly influenced by an etching rate of an etching apparatus during an etching operation, so that it will considerably fluctuate. In an SGT, a fluctuation in height dimension of a pillar-shaped silicon layer has a direct impact on a fluctuation in channel length, which causes a considerable fluctuation in transistor characteristics.
Secondly, in the above process flow, dry etching for a gate electrode also has to be performed under etching conditions including a designated etching time, because it is unable to employ the end-point detection process based on monitoring of a change in plasma emission intensity. In this case, a gate length is directly influenced by an etching rate of an etching apparatus during an etching operation, so that it will considerably fluctuate. The fluctuation in gate length inevitably causes a considerable fluctuation in transistor characteristics.
Thus, in the above SGT production method, due to considerable influence of the etching rate during the etching operation on the height dimension and the gate length of the pillar-shaped silicon layer, it is extremely difficult to minimize a fluctuation in transistor characteristics between wafers or production lots.

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first embodiment

[0044]A first embodiment of the present invention provides a method for, in an operation of forming a pillar-shaped silicon layer by dry etching, accurately controlling an etching amount of the pillar-shaped silicon layer, using an end-point detection process based on monitoring of a plasma emission intensity.

[0045]FIG. 1(a) is a top plan view showing an NMOS SGT produced by the method according to the first embodiment, and FIG. 1(b) is a sectional view taken along the line A-A′ in FIG. 1(a). With reference to FIGS. 1(a) and 1(b), the SGT produced by the method according to the first embodiment will be described below.

[0046]A pillar-shaped silicon layer 102 is formed on a silicon substrate 101, and a gate dielectric film 105 and a gate electrode 106a are formed around the pillar-shaped silicon layer 102. An N+ drain diffusion layer 103 is formed underneath the pillar-shaped silicon layer 102, and an N+ source diffusion layer 104 is formed on a top of the pillar-shaped silicon layer ...

second embodiment

[0055]A second embodiment of the present invention provides a method for, in an operation of forming a gate electrode by dry etching, accurately controlling an etching amount of the gate electrode, using an end-point detection process based on monitoring of a plasma emission intensity. An SGT to be produced by the method according to the second embodiment has the same structure as that illustrated in FIGS. 1(a) and 1(b).

[0056]FIGS. 7(a) to 14(b) show one example of the SGT production method based on accurate etching for a gate electrode. In FIGS. 7(a) to 14(b), the figure suffixed with (a) is a top plan view, and the figure suffixed with (b) is a sectional view taken along the line A-A′ in the figure suffixed with (a).

[0057]FIGS. 7(a) and 7(b) show a configuration before forming a gate conductive film. An N+ diffusion layer 103 is formed in a diffusion region beneath a pillar-shaped silicon layer, by impurity implantation or the like.

[0058]As shown in FIGS. 8(a) and 8(b), a gate die...

third embodiment

[0067]A third embodiment of the present invention provides another method for, in an operation of forming a gate electrode by dry etching, accurately controlling an etching amount of the gate electrode, using an end-point detection process based on monitoring of a plasma emission intensity. An SGT to be produced by the method according to the third embodiment has the same structure as that illustrated in FIGS. 1(a) and 1(b).

[0068]FIGS. 7(a) to 14(b) show one example of the SGT production method based on accurate etching for a gate electrode. In FIGS. 7(a) to 14(b), the figure suffixed with (a) is a top plan view, and the figure suffixed with (b) is a sectional view taken along the line A A′ in the figure suffixed with (a).

[0069]FIGS. 15(a) and 15(b) show a sectional structure after forming a gate conductive film. In the third embodiment, the gate conductive film comprises a first gate conductive film, a second gate conductive film and a third gate conductive film. The first gate con...

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Abstract

In a conventional SGT production method, during dry etching for forming a pillar-shaped silicon layer and a gate electrode, an etching amount cannot be controlled using an end-point detection process, which causes difficulty in producing an SGT while stabilizing a height dimension of the pillar-shaped silicon layer, and a gate length. In an SGT production method of the present invention, a hard mask for use in dry etching for forming a pillar-shaped silicon layer is formed in a layered structure comprising a first hard mask and a second hard mask, to allow the end-point detection process to be used during the dry etching for the pillar-shaped silicon layer. In addition, a gate conductive film for use in dry etching for forming a gate electrode is formed in a layered structure comprising a first gate conductive film and a second gate conductive film, to allow the end-point detection process to be used during the dry etching for the gate electrode.

Description

RELATED APPLICATIONS[0001]Pursuant to 35 U.S.C. §119(e), this application claims the benefit of the filing date of Provisional U.S. Patent Application Ser. No. 61 / 207,554 filed on Feb. 13, 2009. This application is a continuation application of PCT / JP2009 / 052144 filed on Feb. 9, 2009 which claims priority under 35 U.S.C. §365(a) to PCT / JP2008 / 052150 filed on Feb. 8, 2008. The entire contents of these applications are hereby incorporated by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a production method for a semiconductor device, and more particularly to a production method for an SGT (Surrounding Gate Transistor) which is a vertical MOS transistor comprising a pillar-shaped semiconductor layer having a sidewall serving as a channel region, and a gate electrode formed to surround the channel region.[0004]2. Description of the Related Art[0005]With a view to achieving higher integration and higher performance of a semicon...

Claims

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Application Information

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IPC IPC(8): H01L21/66
CPCH01L21/823885H01L22/26H01L29/0692H01L29/78642H01L29/42392H01L29/4908H01L29/66666H01L29/42356
InventorMASUOKA, FUJIOARAI, SHINTARO
OwnerUNISANTIS ELECTRONICS SINGAPORE PTE LTD