Method of manufacturing semiconductor device and substrate processing apparatus

a technology of semiconductor devices and processing equipment, which is applied in the direction of liquid surface applicators, coatings, chemical vapor deposition coatings, etc., can solve the problems of degrading and achieve the effect of preventing the degradation of the quality of the substrate or the performance of the semiconductor devi

Inactive Publication Date: 2013-06-13
KOKUSA ELECTRIC CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention aims to provide a method and apparatus for manufacturing a semiconductor device that prevents degradations in substrate quality and performance.

Problems solved by technology

However, pollutants or particles may be generated during polishing of a surface of a silicon film and may then be mixed with a substrate including the silicon film.
In this case, the quality of the substrate or the performance of a semiconductor device may be degraded.

Method used

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  • Method of manufacturing semiconductor device and substrate processing apparatus
  • Method of manufacturing semiconductor device and substrate processing apparatus
  • Method of manufacturing semiconductor device and substrate processing apparatus

Examples

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first embodiment

[0017]Hereinafter, the first embodiment of the present invention will be described in detail with reference to the appended drawings. FIG. 1 is a perspective view of a semiconductor manufacturing apparatus 10 as a substrate processing apparatus according to the first embodiment of the present invention. The semiconductor manufacturing apparatus 10 is a batch-type vertical heat treatment apparatus and includes a housing 12 in which main parts are disposed. In the semiconductor manufacturing device 10, a Front Opening Unified Pod (FOUP) (hereinafter referred to as a pod) 16 which is a substrate receiver that receives a wafer 200 as a substrate formed of, for example, silicon (Si) or silicon carbide (SiC) is used as a wafer carrier. A pod stage 18 is disposed in front of the housing 12, and the pod 16 is conveyed to the pod stage 18. For example, 25 sheets of wafers 200 are received in the pod 16, and the pod 16 is dosed with a cover and then placed on the pod stage 18.

[0018]In the hou...

second embodiment

[0082]Next, a second embodiment of the present invention will be described. The second embodiment is a modified example of the first embodiment of the present invention, in which nucleus formation is performed to form a film after repeatedly performing one cycle including a nucleus growth suppression process and a nucleus formation process twice or more, as will be described in detail below.

[0083]Each of the processes will now be described in detail.

[0084]

[0085]As described above, while silicon nuclei are formed on the wafer 200, the growth of the formed silicon nuclei is controlled by supplying a chlorine-containing gas for a predetermined time.

[0086]Although, in the present embodiment, dichlorosilane gas (SiH2Cl2) is used as the chlorine-containing gas, the present invention is not limited thereto. For example, trichlorosilane gas (SiHCl3), tetrachlorosilane gas (SiCl4), chlorine gas (Cl2), hydrogen chloride gas (HCl), or a combination thereof may be used.

[0087]As an example, in t...

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Abstract

A film is formed on a substrate by performing a cycle at least twice, the cycle including a nucleus formation process for forming nuclei on the substrate and a nucleus growth suppression process for suppressing growth of the nuclei. A time required for the nucleus growth suppression process is less than or equal to a time required for the nucleus formation process. Alternatively, the nucleus formation process is further performed after the cycle is repeatedly performed a plurality of times.

Description

CROSS-REFERENCE TO RELATED PATENT APPLICATION[0001]This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Japanese Patent Application No. 2010-195662, filed on Sep. 1, 2010, in the Japanese Patent Office, and International Patent Application No. PCT / JP2011 / 069319, filed on Aug. 26, 2011, in the WIPO, the entire contents of which are hereby incorporated by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a method of manufacturing a semiconductor device including a substrate processing process, and a substrate processing apparatus, and more particularly, to a method of manufacturing a semiconductor device including forming a silicon film and a substrate processing apparatus.[0004]2. Description of the Related Art[0005]In one process of a manufacturing process of a semiconductor device, a NAND flash memory developed after 2X-nm NAND flash memory has been suggested to be applied to a terabit cell arr...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L21/02
CPCC23C16/0236C23C16/24H01L21/0245H01L21/02532H01L21/0262C23C16/45523C23C16/45544C23C16/52H01L21/02592
InventorKOSHI, YASUNOBUNISHIDA, KEIGOMAEDA, KIYOHIKO
OwnerKOKUSA ELECTRIC CO LTD