Cascaded pll for reducing low-frequency drift in holdover mode

Abstract

A cascaded phase-locked loop (PLL) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first PLL circuit configured to generate a control signal based on a first clock signal and a first divider value. The apparatus includes a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value. The apparatus includes a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. The low-jitter clock signal may have a greater temperature dependence than the second clock signal and the second clock signal may have a higher jitter than the low-jitter clock signal.

Description

BACKGROUND[0001]1. Field of the Invention[0002]This invention relates to integrated circuits and more particularly to clock generator integrated circuits.[0003]2. Description of the Related Art[0004]High speed communication systems require high speed clock signals for transmission and reception of information. In a typical clock generation circuit, a phase-locked loop (PLL) receives a synchronization input reference clock signal and generates one or more high speed clock signals suitable for use in transmitting or receiving data. According to one aspect of such a communication system, when the synchronization input reference clock signal is lost, the system enters a mode known as “holdover” mode and continues to output a clock signal.[0005]The accuracy with which the clock generation circuit provides the clock signal in holdover mode is typically specified in a system standard. The clock generation circuit tries to maintain the output clock signal during holdover mode at a frequency...

AI Technical Summary

Benefits of technology

[0007]A cascaded phase-locked loop (PLL) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. In at least one embodiment of the invention, an apparatus includes a first PLL circuit configured to generate a control signal based on a first clock signal and a first divider value. The apparatus includes a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value. The apparatus includes a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. The first PLL may generate an output clock signal based on the control signal and the first clock signal. The first PLL may provide the control signal to the third PLL circuit as the third divider value and may provide the first clock signal as an output clock signal. The low-jitter clock signal may have a greater temperature dependence than the second clock signal and the second clock signal may have a higher jitter than the low-jitter clock signal. In a normal mode, the control signal may be based on a control value generated by the first PLL in response to a valid input clock signal. In a holdover mode, the control signal may be based on a held control value generated by the first PLL in the normal mode, prior to entering a holdover mode.

Problems solved by technology

However, the frequency of the clock signal generated in holdover mode may still drift to such an extent as to fail to meet the holdover requirements.

For example, certain PLLs may fail to meet holdover requirements because the voltage controlled oscillators utilized in such systems have too much frequency variation over temperature (e.g., 100 ppm / ° C.).

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