Phase locked circuit, method of operating the same, and transceiver

Abstract

A phase locked circuit includes an oscillator configured to generate an output clock signal, a first phase detector configured to detect a phase difference between an input clock signal and a feedback clock signal based on the output clock signal, a second phase detector having a wider phase locking range than that of the first phase detector and configured to detect the phase difference between the input clock signal and the feedback clock signal, and a charge pump controller configured to control an output current of a charge pump included in the second phase detector based on the phase difference detected by the first phase detector. When the phase difference between the input clock signal and the feedback clock signal is within the phase locking range of the first phase detector, the oscillator and the first phase detector are connected to each other.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This U.S. non-provisional patent application claims the benefit of under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0083948, filed on Jul. 11, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein.BACKGROUND1. Technical Field[0002]The inventive concept relates to a phase locked circuit, and more particularly, to a phase locked circuit including a fine phase detection circuit and a coarse phase detection circuit.2. Discussion of Related Art[0003]A phase locked circuit (a phase locked loop (PLL)) is a control system that generates an output signal whose phase is related to the phase of a reference signal. The phase locked circuit may synchronize and fix the phase of the reference signal with the phase of the output signal. The phase locked circuit may include a phase detection circuit used for synchronizing and fixing a phase difference between the referenc...

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