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Data error check method and relative device

A technique of error checking and data error, applied in the direction of error detection of redundant codes, generation of response errors, etc.

Active Publication Date: 2008-07-02
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Moreover, as known to those skilled in the art, 32-bit data may require 6-bit error checking code to achieve error checking. In contrast, the error checking of 64-bit data / 8-bit error checking code is much more economical

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  • Data error check method and relative device
  • Data error check method and relative device
  • Data error check method and relative device

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Embodiment Construction

[0032] refer to figure 1 ; figure 1 It is a functional block diagram of a computer system 10 in the present invention. The computer system 10 can be provided with a CPU 12 , a chipset 16 , a memory 18 and peripheral circuits 14 . The CPU 12 is used to execute programs, process data and calculate data, and the memory 18 is used to store programs, data and data required during the operation of the CPU 12 . The peripheral circuit 14 can be a hard disk drive, a CD-ROM, or various add-in cards (such as a display card, a network card, a sound card, etc.), and the chipset 16 is used to manage the pair memory of the central processing unit 12 and the peripheral circuit 14. 18 access, and perform data check / correction when accessing the memory 18, to realize the data checking mechanism.

[0033] As mentioned above, the memory in the computer system may include a memory module structured as a memory unit, and in figure 1 In the embodiment, a plurality of (N) storage units 36 and a s...

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Abstract

The invention discloses method and relevant device for carrying out checking and correcting data error in accessing memory. In the optimized instance, the invention can fetch multiple data and multiple checking codes. The multiple data can be regarded as an integrated data, and multiple checking codes can be regarded as an integrated checking data, which can be utilized to check and correct said integrated data, or that is equivalent to check and correct original multiple data. For example, in case of accessing memory in doubling data rate under 32 bits data architecture, the invention regards two pieces of 32 bits data fetched in same clock cycle as a piece of 64 bits data. Moreover, checking of data error under 32 bits architecture can be realized by using algorithm in use for 64 bits data / 8 bits checking codes.

Description

technical field [0001] The invention provides a data error checking method and a related system, especially a method and a related system for error checking / correcting when accessing a memory with a high data rate. Background technique [0002] In the modern information society, computer systems have been widely used in every aspect of social life. In addition to general applications such as personal computers and servers, terminals for financial services such as cash machines (ATMs) and some multi-functional Item / ticket vending machines and various information home appliances are also equipped with embedded computer systems. Under different applications, different computer systems may also have different system requirements. For example, personal computers / servers pay more attention to high performance and expandability; in contrast, financial service terminals such as cash machines pay more attention to the correctness of data access, and do not need to pay attention to e...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/08
Inventor 林景祥江蕙如丁杰
Owner VIA TECH INC
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