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Multi-interruption cache device and method

A cache and memory technology, applied in the field of data transmission, can solve the problem of low memory utilization, avoid blockage and vacancy, improve utilization efficiency, and improve efficiency.

Inactive Publication Date: 2008-09-17
VIMICRO CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] In view of this, in order to solve the problems of low memory utilization rate, not being interrupted by non-emergency events, and not missing urgent write / fetch interrupts, the present invention proposes a device and method for using multi-interrupt cache

Method used

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Embodiment Construction

[0033] The key point of the present invention is to propose that the interrupt generating unit 200 can generate multiple interrupts. Such as figure 2 As shown, the upper layer software 203 of the memory control unit can set each condition register 2001, condition register 2002, and condition register 2003 through software. The register 20033 is compared with the condition register 2001, the condition register 2002 and the condition register 2003, and a corresponding interrupt is generated if the condition is met.

[0034] Such as image 3 As shown, taking the memory in the general sense as an example, it is assumed that in this cache device, the interrupt generation unit 212 of the sender and the interrupt generation unit 222 of the receiver can generate three interrupts. The first one is when the stored data reaches the capacity of the memory 201 1 / 4 of the time, the interrupt generation unit 212 of the sender generates an interrupt to the sender 211, and the priority of t...

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Abstract

The invention discloses a multi-interrupt buffer and method. The buffer comprises storage, a storage control unit and an interrupt occurring unit. It allocates an interrupt generating unit register to the interrupt occurring unit to control the interrupt occurring unit to generate the interrupt. The method comprises the following steps: arranging each interrupt generating condition register, arranging the interrupt occurring unit making register, sending data, triggering the interrupt occurring unit when the storage unit achieves to a special position, generating the interrupt by the interrupt occurring unit to give the corresponding device, quoting weather processing the interrupt by the interrupt priority, processing the interrupt, sending or receiving the data.

Description

technical field [0001] The invention relates to data transmission technology, in particular to an improved cache device and method used in data transmission. Background technique [0002] In the system design with data transmission, different devices are selected in the system design. Because different devices have different data processing data, the data transmission between each device is not coordinated. In order to solve this problem, many system designs currently Both of them choose the buffer method to coordinate this problem. [0003] Interrupt, DMA and channel control techniques are used in the system design to make each device in the system work in parallel. However, the problem that the processing speed of the equipment does not match is an objective existence. This limits the number of connections between devices. [0004] The problem that the device does not match the speed of the device can be solved by setting a buffer. After the buffer is set, the data out...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/26
Inventor 张怡浩
Owner VIMICRO CORP
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