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Interpretation method and apparatus for tail-biting convolutional code

A tail-biting convolutional code and decoding technology, applied in the direction of error correction/detection using convolutional codes, data representation error detection/correction, etc. Fixed the amount of calculation and other problems, to achieve the effect of saving decoding delay and saving calculation amount

Inactive Publication Date: 2009-02-18
HUAWEI TECH CO LTD
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

[0022] In the process of implementing the present invention, the inventor found that the implementation in the prior art has the following problems: the decoding delay and calculation amount of the existing Viterbi decoding algorithm of the tail-biting convolutional code are fixed, even when the channel quality is very low. Well, when there are few errors in the received sequence, it is necessary to calculate L TB blocks before generating the decoding output. In fact, it is possible to obtain the correct decoding output with only a few TB blocks. Therefore, the existing method increases Calculation amount and decoding delay

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Embodiment Construction

[0040] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0041] A decoding method of a tail-biting convolutional code is provided in an embodiment of the present invention, such as image 3 shown, including:

[0042] Step s301, performing Viterbi decoding on the sequence obtained after repeating the same transmission block multiple times and concatenating it end to end, after decoding each transmission block in the sequence, judge whether the output condition is satisfied according to the maximum path obtained by the decoding .

[0043] Step s302, when it is judged that the output condition is met, the maximum path is used as a traceback path to obtain the decoded data of the long sequence.

[0044]In the embodiment of the present invention, according to the first and last state of th...

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Abstract

Embodiment of the present invention discloses a decoding method and apparatus for tail-biting convolution code. The method includes the steps of implementing Viterbi decode to a sequence obtained by repeating a transmission block end-to-end for multiple times, wherein after decoding each transmission block of the sequence, judging whether meeting output condition based on a maximum path obtained by the decode; when meeting output condition, outputting decode data of the sequence using the maximum path as backtracking path. In the embodiment of the invention, judging the Viterbi decode of a long sequence obtained by linking a plurality of transmission blocks based on the head end status of the maximum path, when meeting presetting output condition, a decode data can be obtained directly without calculating all transmission blocks, thus it is able to obtain right decode output using less transmission blocks, and computational complexity and decode time delay are all saved.

Description

technical field [0001] The present invention relates to the field of communication technology, in particular to a decoding method and device for a tail-biting convolutional code. Background technique [0002] In the prior art, the encoding and modulation method of the tail-biting convolutional code is proposed, and the tail-biting convolutional code used in the LTE (Long Term Evolution, Long Term Evolution) system is used as an example for illustration. The (3, 1, 6) encoder is as follows: figure 1 shown. [0003] The encoder has a constraint length of 7 and a code rate of 1 / 3. figure 1 Generator polynomial G in i The binary sequence of (i=0, 1, 2) represents the input data and the connection status of the 6 shift registers and the i-th output of the encoder. Binary 0 means not connected, binary 1 means connected. figure 1 The middle adder is performed in the GF(2) field. The initial state of the shift register is the last 6 bits of the input bit sequence, so that η 0 ...

Claims

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Application Information

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IPC IPC(8): H03M13/23
Inventor 魏璟鑫
Owner HUAWEI TECH CO LTD
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