Dual bootstrap and voltage compensation technology-based A/D converter sampling switch

Abstract

The present invention discloses a dual bootstrap and voltage compensation technology-based A / D converter sampling switch, which comprises a primary switch unit used for a to-be-sampled signal channel to sample to-be-sampled signals, an underlayer voltage bootstrap unit for realizing the underlayer voltage bootstrap of a switching tube PMOS Switch in the primary switch unit, a grid voltage bootstrap unit for realizing the grid voltage bootstrap of the switching tube PMOS Switch in the primary switch unit, a storage unit for parallelly sampling input signals VIN and realizing the temporary storage of a VIN voltage, and a voltage compensation unit for compensating the sampling output voltage of an output end VOUT. The invention provides a sampling switch which is capable of working at low voltage and low power consumption and is insensitive to process errors. Meanwhile, the adopted voltage self-compensation method effectively solves a nonlinear problem caused by clock feed through occurring after the grid voltage bootstrap of the switching tube.

Description

technical field [0001] The invention relates to the technical fields of microelectronics and solid electronics, in particular to a low-voltage high-linearity A / D converter sampling switch based on double bootstrap and voltage compensation technologies. Background technique [0002] 1. Bootstrap switch and its accuracy limitations [0003] Analog-to-digital A / D (Analog-to-Digital) converter is an essential interface between analog signal and digital signal in all electronic systems, and its conversion accuracy directly affects the overall performance index of the entire electronic system. [0004] At present, in order to adapt to the rapid development of computer, communication and multimedia technologies, A / D converters have made great progress in technology, structure and performance, and are developing in the direction of low power consumption, high speed and high resolution. The sampling circuit is a crucial unit in the A / D converter, and its performance directly determi...

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Problems solved by technology

[0008] Two problems can be found from the formula: first, assuming that the threshold voltage V of the switch TH When constant, R ON is the one with the input signal V IN related non-linear resistance, which will cause non-linear distortion of the output signal. For occasions that require high sampling accuracy, the impact of the distortion introduced by the sampling switch on the system accuracy cannot be ignored; second, only When the gate voltage V Gate with source input V IN When the difference is greater than the threshold voltage of the switch, the switch can be turned on normally, which makes V IN The value must satisfy V IN Gate -V TH , this requirement would greatly limit the range of the input signal

[0021] However, this solution has the following problems: first, M2 cannot completely replicate the working state of M1 tube, because M2 is always working in a saturated state, and M1 tube is going through multiple working states under the action of a large signal, and at the same time according to V IN and V OUT The relationship between the two MOS tubes changes continuously with the signal, and there will be a problem of source-drain terminal interchange, and they will work in a non-saturated region before they are finally turned off, which will inevitably make the V of the two MOS tubes TH cannot be exactly the same; secondly, when considering the short channel effect, V TH vs. source-drain voltage V DS related, while M1 and M2 are V DS are not the same, will result in V TH It will not be exactly the same; finally, it is also very important that this scheme needs to introduce an amplifier, which will inevitably have a quiescent operating current, which greatly increases the complexity and power consumption of the switch, and limits its application range

[0023] For this scheme, there are the following problems: First, due to the constant change of the input signal, the distinction between the source and drain terminals of the switch tube is not clear, and when V OUT When it is the source terminal, if the level of the previous sampling is much higher than the input signal of this time, it may occur that the source and the substrate PN junction are forward biased; secondly, this scheme requires two consecutive gate voltages Bootstrapping, the conduction of M4 needs to be completed by bootstrapping C2, after which the gate of the switch MS can be bootstrapped to the required voltage, which reduces the upper limit of the switching speed to a certain extent, plus the bootstrapping of C2 The effect is easily affected by parasitic capacitance and process deviation, which makes the actual use effect of this scheme greatly reduced

In high-speed and high-precision applications, the size of the switching MOS transistor is generally large, and the influence of parasitic capacitance is more significant. Clock breakdown will become a new source of nonlinear distortion, and the existing bootstrap switch solutions cannot solve it. this question

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